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Trapped charge dynamics in InAs nanowires
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) Conductance through an InAs nanowire FET as gate voltage is swept from negative to positive values. The two visible jumps are caused by electron capture events in two different charge traps. (b) Random telegraph signal in the FET conductance versus time, showing two-level behaviour. The electron capture and emission times, and , correspond to the high and low conductance states, respectively.

Image of FIG. 2.
FIG. 2.

(a) Energy level diagram describing a trap model consistent with our data. EF and EC are energies of the Fermi level and the conduction band in the nanowire. The vertical dotted line separates the nanowire and its native oxide. The dashed parabolas represent the quadratic dependence of the electron-lattice interaction energy on the configuration coordinate (not shown), which leads to the multiphonon emission barrier 4 of energy EB . ET and are the energies of the filled and empty trap states, respectively. The upper horizontal line indicates the energy of the transition level that is above the conduction band, where is the Coulomb energy. Ecap and Eemis are the energies required for electron capture and emission to occur. Ecap varies linearly with , whereas Eemis is independent of . (b) and (c) Variation in the average capture and emission times of two different traps in the same FET device, versus . The fits (solid lines) described in the text yield the energy barriers associated with capture and emission.

Image of FIG. 3.
FIG. 3.

(a) and (b) Average capture and emission times as a function of gate voltage VG . The weak dependence of the emission time on VG is consistent with a model of neutral/negative charge traps. The dependence of on VG is used to extract an upper bound on the radial distance of the trap relative to the nanowire surface.

Image of FIG. 4.
FIG. 4.

(a) Conductance curves for a 32 nm diameter nanowire FET measured at 50 K, with several initial gate voltages Vi applied during cooldown from K. When a positive Vi is applied, traps are predominantly filled and pinchoff occurs at a more positive gate voltage. Here “traps” may refer to other defects beyond native oxide charge traps, such as InAs surface states or SiO2 charge traps. (b) Change in pinchoff threshold voltage VT versus Vi . The saturation that occurs at positive Vi suggests most traps are being filled. No saturation was seen for negative voltages down to −9 V, suggesting that only a fraction of traps were depleted.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Trapped charge dynamics in InAs nanowires