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Electronic properties of light-emitting p-n hetero-junction array consisting of p+-Si and aligned n-ZnO nanowires
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10.1063/1.4792302
/content/aip/journal/jap/113/8/10.1063/1.4792302
http://aip.metastore.ingenta.com/content/aip/journal/jap/113/8/10.1063/1.4792302
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Fabrication processes of a p+-Si/n-ZnO NWs hetero-junction devices: ① Patterning of SiO2 layer to have trench structures with SiO2 shoulders by photolithography technique. ② Deposition of Al electrodes on p+-Si and thermal annealing. ③ Aligning ZnO NWs via sliding transfer technique. ④ Deposition of Ti/Au electrodes on ZnO NWs. ⑤ Spin coating of PVP dielectric layer and e-bam evaporation of Ti/Au top gate electrode.

Image of FIG. 2.
FIG. 2.

(a) SEM image of p+-Si/n-ZnO NWs hetero-junction array with top gate. The inset is a zoomed image. (b) SEM image of the p+-Si/ n-ZnO NW hetero-junction. Upper left inset shows a cross-sectional SEM image of a bent ZnO NW across the patterned SiO2 shoulder, contacting the underlying p+-Si substrate. Upper right inset outlines the cross-section of the hetero-junction. (c) Current-voltage (I-V) characteristics of the hetero-junction. Inset shows I-V curves taken from the individual p+-Si and ZnO NW channels. (d) dI/dV vs. 1/I derived from the data (c) and a fitting with equivalent circuit model of serially connected diode and resistor.

Image of FIG. 3.
FIG. 3.

(a) I-V curves with varying gate bias. Inset shows the top-gated p+-Si/n-ZnO NW hetero-junction device. (b) Turn-on voltage of the hetero-junction device with respect to gate bias. (c) Electronic band diagrams at the hetero-junction under forward bias: Upper, Vg = −5 V and lower, Vg = +5 V.

Image of FIG. 4.
FIG. 4.

(a) UV photosensitivity (Iph/Idark) of the hetero-junction with respect to bias voltage. Inset shows reverse current under UV irradiation (Ilight) of varying intensity (P). (b) UV photosensitivity (Iph/Idark) of the ZnO NW FET with respect to gate bias. Inset shows the structure of bottom-gated ZnO NW FET.

Image of FIG. 5.
FIG. 5.

(a) Top left: SEM image showing a large-scale line pattern of p+-Si/n-ZnO NWs hetero-junction. The inset is the zoomed SEM image. The photographs from top-right to bottom-right in the counter-clockwise direction are the luminescence patterns taken by increasing the bias voltage from +8 to +14 V. (b) EL spectra of hetero-junction arrays with respect to bias voltage. Inset shows the photoluminescence spectrum of the ZnO NWs. (c) Deconvolution of the visible EL spectrum taken at a bias of +14 V, showing three Gaussian peaks. (d) Energy band diagram of the hetero-junction under +8 V forward bias.

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/content/aip/journal/jap/113/8/10.1063/1.4792302
2013-02-27
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Electronic properties of light-emitting p-n hetero-junction array consisting of p+-Si and aligned n-ZnO nanowires
http://aip.metastore.ingenta.com/content/aip/journal/jap/113/8/10.1063/1.4792302
10.1063/1.4792302
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