(a) Schematic showing the key features of a TFET with Ge/In0.53Ga0.47As tunneling junction. (b) Energy band diagrams illustrating the tunneling junction regions in two TFETs. The first TFET has a homojunction where the tunneling path length is LT ,1. The second TFET has a heterojunction with type II or staggered band alignment, and the tunneling path length LT ,2 is smaller than LT ,1 under the same bias condition.
IDS -VGS curves for In0.53Ga0.47As TFET and TFET with Ge/In0.53Ga0.47As tunneling junction at VDS = 0.5 V. ION and S of TFET are improved by employing Ge/In0.53Ga0.47As heterojunction as tunneling junction.
Process steps used in the fabrication of Ge-source In0.53Ga0.47As-channel TFET: (a) deposition of a 20 nm thick sacrificial ALD Al2O3; (b)Si+ implantation to form n+ doped drain region; (c) recess etching into In0.53Ga0.47As followed by selective growth of p+ Ge by MOCVD; (d) formation of gate stack comprising TaN on Al2O3.
(a) High-resolution XRD curve of a blanket Ge/In0.53Ga0.47As sample. The Ge peak was clearly observed. The peaks from In0.53Ga0.47As and InP substrate appear at the same Bragg angle due to the same lattice constant. (b) The RMS surface roughness for a 5 μm × 5 μm area is 0.54 nm, indicating that a smooth Ge surface was obtained.
(a) High-resolution TEM image of 50 nm thick Ge epitaxially grown on In0.53Ga0.47As substrate. (b) TEM image at the Ge/In0.53Ga0.47As interface indicated by the dashed box in (a). High quality Ge film was formed and defects were only observed at the interface.
Raman spectra of a bulk Ge sample and a In0.53Ga0.47As sample topped by 50 nm thick Ge film. Lorentzian functions were fitted to the spectra. The small shift of the Ge peak with respect to that of bulk Ge indicates the epitaxial Ge film is almost fully relaxed.
SIMS analysis of the Ge/In0.53Ga0.47As sample indicates that Ge atoms diffuse into In0.53Ga0.47As. As a result, an n-type In0.53Ga0.47As layer is formed at the Ge/In0.53Ga0.47As interface. This n-type layer enhances the lateral electric field at the tunneling junction, which can contribute to a higher TFET drive current.
(a) Top-view SEM image of a fabricated TFET. (b) Zoomed-in view of the same device in (a). The gate-to-source overlap LOV , GS of 5 μm is clearly observed. The channel length LCH is 8 μm. (c) TEM image of a fabricated TFET device showing the tunneling junction region.
(a) The Ge 3d core-level and valence band spectra for 50 nm thick Ge on In0.53Ga0.47As. (b) The As 3d core-level and valence band spectra for In0.53Ga0.47As reference sample. The valence band maximum is extrapolated from the intersection point between the leading edge of the valence band spectrum and the base line. (c)The Ge 3d and As 3d core-level spectra from the Ge on In0.53Ga0.47As sample after Ge was thinned down by Ar ion. Energy difference between the two core-levels is shown. (d) The energy band alignment between Ge and In0.53Ga0.47As is illustrated, showing the conduction band offset of 0.2 ± 0.1 eV and valence band offset of 0.5 ± 0.1 eV. The band gap narrowing effect due to high doping concentration in Ge was taken into consideration.
IDS -VGS characteristics of a Ge-source In0.53Ga0.47As-channel TFET with LCH of 8 μm. The LOV , GS and LOV , GD are 9 μm and 2 μm, respectively. The minimum point S is ∼177 mV/decade. (b) IDS -VD S characteristics of the same device in (a). The device performance can be further improved by optimizing the Ge/In0.53Ga0.47As tunneling junction.
IDS -VGS characteristics of a fabricated TFET under various temperatures ranging from 240 K to 330 K in steps of 30 K.
(a) Arrhenius plot of ln(IOFF /T 3/2) versus 1/kT. The slope of the fitted line is ∼0.27 eV, which corresponds to the half band gap of Ge, indicating the off-state leakage current floor is determined by the SRH generation-recombination current in the source side. (b) Plot of ION and S as a function of temperature. The ION increases as temperature changing from 240 K to 330 K, which is mainly due to the band gap reduction. Due to the trap assisted tunneling, S has a positive temperature dependence. The discrepancy of the S at room temperature between this transistor and the one in Fig. 10 was due to device-to-device variation.
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