(a) and (b) High resolution TEM images revealing single crystal structure and a thin oxide layer (2–5 nm) on the surface of the nanowire. (c)Diffraction pattern verifying the zinc-blende structure of InP nanowire. (e) High resolution TEM image optimized to enhance the Z-contrast between an ∼2 nm In-rich crystalline region at the surface of the nanowire.
2-probe and 4-probe I–V measurements show that contact resistances are less than 0.05 MΩ. Left-top inset: SEM image of single nanowire FET device with 4 electrodes. Right bottom inset: I vs. Vg showing saturation current at negative gate voltage (|Vg | is limited to less than 30 V to avoid significant leakage current).
(a) Temperature dependent I–V plots and fitting to Schottky model (ideality factor ranges from 97 to 73). Inset is the semi-log plot of showing non-exponential function dependence on Vs-d . Temperature is varied from 150 K to 300 K in 30 K increments. (b) A log-log plot of the same data shows linear behavior, I ∼ VS , with slope increasing as temperature decreases (add 120 K and 100 K plots). The extrapolations of the linear fits converge to a crossover point (Vc , solid lines taken at > 150 K). Inset is a band-structure plot of the InP −1 defect using GGA.
(a) Log-log plot of ln(R) vs. 1/T. The graph shows that there is a crossover in slope: from mhigh = 1.03 at high temperature to mlow = 0.49 at low temperature (Vg = 0 V). Inset is a cartoon showing NNH at high temperature and ES-VRH at low temperature (see text). (b) Red dot is the low temperature slope deviating from m = 0.5 at Vg > +9 V. Similar gate voltage dependent trends can be seen in the crossover temperature (Tcr ), NNH temperature (TNNH ), and ES-VRH temperature (TES-VRH ) vs. Vg plots.
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