(a) Simulated output characteristics of source-gated devices with device geometry as reported in Ref. 1 and fixed Schottky barrier at source contact (0.5 eV). Also indicated are the Vdsat1 (●) and Vdsat2 (♦) values. (b) Simulated output characteristics at Vgs = 9.2 V and 3.2 V for source-gated devices with device geometry as reported in Ref. 1 , including different barrier lowering mechanisms: Schottky effect 23 (dashed line); thermionic field-emission 24 (dotted line); and no barrier lowering (solid line).
Channel resistance, Rch, deduced from simulations adopting ohmic contacts, and contact resistance, Rc, both evaluated at low-Vds and for different Vgs.
Cut-lines of the current density at the metal-semiconductor interface (see inset) at the source contact reported for different gate bias, from Vgs = 1 V to 10 V step 1 V, and given Vds = 1 V.
Electrostatic potential cut-lines at the semiconductor-insulator interface for different values of Vds and Vgs = 3.2 V. Also indicated near the source end of the channel is the floating source potential of the transistor Vc (○).
Electric field at the metal-semiconductor interface at the source contact edge (x = 5 μm) vs Vds for Vgs = 3.2 V and 9.2 V. Also indicated are the corresponding Vdsat1 values.
Saturation voltage (▪), Vdsat1, for different gate voltages. Also shown is the slope predicted by the two-dielectric model 2 (dashed line).
Current density cut-lines at the metal-semiconductor interface for different Vds and given Vgs = 9.2 V.
(a) SGT output characteristics calculated at Vgs = 7.2 V according to Chiang et al. model 25 (dotted line) and compared with the characteristics obtained from numerical simulations (○). Also shown are the SGT output characteristics obtained using the distributed diode model (dashed lines) and the output characteristics calculated according to Eqs. (2) and (3) and using the estimated Vdsat1 values (continuous line). In (b) an expanded view of the output characteristics around the origin.
Schematic of the equivalent circuit representing the distributed diode model of the source contact, where rch is the channel resistance per unit channel length, rb is the semiconductor bulk resistivity, and the non-ohmic injection resistivity is represented by a distributed diode network. Also shown at the source edge of the channel is the additional effective diode introduced to model the device characteristics above Vdsat1.
Electric field at the metal-semiconductor interface, , vs the potential drop across the semiconductor active layer, ΔV, deduced from the difference between the quasi Fermi level at the insulator/semiconductor interface and the metal/semiconductor interface, both evaluated for same x.
Comparison of SGT output characteristics at different Vgs obtained from numerical simulations (○) with those calculated according to the distributed diode model, using Eqs. (2) and (3) with the estimated Vdsat1 values (solid lines).
Electric field at the metal-semiconductor interface, , and the ratio J0 /JTE, where J0 is the diode reverse current and JTE is the thermionic emission limit for J0 ( ≫ vR/μn) both plotted against drain current.
Potential drop over the channel region, Vdc=Vd − Vc, vs the applied Vds for different Vgs values. By linear extrapolation at Vdc = 0 V the pinch-off voltage for the drain, Vdsat2, can be determined. The obtained Vdsat2 values have been indicated in Fig. 1(a) .
List of parameters used in the numerical simulations.
Article metrics loading...
Full text loading...