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Principle of operation and modeling of source-gated transistors
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Image of FIG. 1.
FIG. 1.

(a) Simulated output characteristics of source-gated devices with device geometry as reported in Ref. and fixed Schottky barrier at source contact (0.5 eV). Also indicated are the V (●) and V (♦) values. (b) Simulated output characteristics at V = 9.2 V and 3.2 V for source-gated devices with device geometry as reported in Ref. , including different barrier lowering mechanisms: Schottky effect (dashed line); thermionic field-emission (dotted line); and no barrier lowering (solid line).

Image of FIG. 2.
FIG. 2.

Channel resistance, R, deduced from simulations adopting ohmic contacts, and contact resistance, R, both evaluated at low-V and for different V.

Image of FIG. 3.
FIG. 3.

Cut-lines of the current density at the metal-semiconductor interface (see inset) at the source contact reported for different gate bias, from V = 1 V to 10 V step 1 V, and given V = 1 V.

Image of FIG. 4.
FIG. 4.

Electrostatic potential cut-lines at the semiconductor-insulator interface for different values of V and V = 3.2 V. Also indicated near the source end of the channel is the floating source potential of the transistor V (○).

Image of FIG. 5.
FIG. 5.

Electric field at the metal-semiconductor interface at the source contact edge (x = 5 μm) vs V for V = 3.2 V and 9.2 V. Also indicated are the corresponding V values.

Image of FIG. 6.
FIG. 6.

Saturation voltage (▪), V, for different gate voltages. Also shown is the slope predicted by the two-dielectric model (dashed line).

Image of FIG. 7.
FIG. 7.

Current density cut-lines at the metal-semiconductor interface for different V and given V = 9.2 V.

Image of FIG. 8.
FIG. 8.

(a) SGT output characteristics calculated at V = 7.2 V according to Chiang model (dotted line) and compared with the characteristics obtained from numerical simulations (○). Also shown are the SGT output characteristics obtained using the distributed diode model (dashed lines) and the output characteristics calculated according to Eqs. (2) and (3) and using the estimated V values (continuous line). In (b) an expanded view of the output characteristics around the origin.

Image of FIG. 9.
FIG. 9.

Schematic of the equivalent circuit representing the distributed diode model of the source contact, where r is the channel resistance per unit channel length, r is the semiconductor bulk resistivity, and the non-ohmic injection resistivity is represented by a distributed diode network. Also shown at the source edge of the channel is the additional effective diode introduced to model the device characteristics above V.

Image of FIG. 10.
FIG. 10.

Electric field at the metal-semiconductor interface, , vs the potential drop across the semiconductor active layer, ΔV, deduced from the difference between the quasi Fermi level at the insulator/semiconductor interface and the metal/semiconductor interface, both evaluated for same x.

Image of FIG. 11.
FIG. 11.

Comparison of SGT output characteristics at different V obtained from numerical simulations (○) with those calculated according to the distributed diode model, using Eqs. (2) and (3) with the estimated V values (solid lines).

Image of FIG. 12.
FIG. 12.

Electric field at the metal-semiconductor interface, , and the ratio J /J, where J is the diode reverse current and J is the thermionic emission limit for J (  ≫ v) both plotted against drain current.

Image of FIG. 13.
FIG. 13.

Potential drop over the channel region, V=V − V, vs the applied V for different V values. By linear extrapolation at V = 0 V the pinch-off voltage for the drain, V, can be determined. The obtained V values have been indicated in Fig. 1(a) .


Generic image for table
Table I.

List of parameters used in the numerical simulations.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Principle of operation and modeling of source-gated transistors