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Analysis of short circuit current loss in rear emitter crystalline Si solar cell
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Short circuit current (Jsc) loss in rear emitter crystalline Si solar cell is analyzed in detail by a 2D device simulation and compared with the experimental results. There is a significant loss in Jsc for the rear emitter n-Si solar cell with an n-type doped front surface field (FSF) when the base substrate resistivity is low. It is due to an increase in recombination in the FSF region led by a less barrier height for minority carriers with a lower substrate resistivity. The barrier height less than 0.1 eV causes large loss in Jsc. To achieve higher Jsc for the cells with FSF, the control of the doping concentration in FSF, the substrate thickness, and the barrier height for the minority carriers are important. A rear emitter heterojunction Si solar cell with an amorphous Si passivation layer shows no substrate resistivity dependence on Jsc since an amorphous Si possess a higher barrier height and a long bulk lifetime of more than a few milliseconds.
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