Index of content:
Volume 87, Issue 12, 15 June 2000
- DEVICE PHYSICS (PACS 85)
87(2000); http://dx.doi.org/10.1063/1.373599View Description Hide Description
Nonlinear conduction properties of multiport quantum waveguide-based devices are theoretically investigated. A two dimensional finite element solver for the time independent Schrödinger equation combined with Poisson equation has been developed. It handles arbitrary geometrical designs and potential profiles in the device active zone. Starting from transmission spectra calculated out of equilibrium, current–voltage characteristics of a quantum branch line directional coupler are derived as a function of the chemical potential of the injection region and of the applied bias between the input and output terminals of the structure. Under the approximation of ballistic transport, a detailed analysis of mono- and multimode propagation regimes shows that pronounced negative differential conductance effects combined with real space lateral transfers can be obtained. The robustness of the current–voltage characteristics as a function of temperature is also addressed.
87(2000); http://dx.doi.org/10.1063/1.373600View Description Hide Description
Nonuniform point-defect generation in n-channel metal–oxide–semiconductor field-effecttransistors under channel-hot-electron stress conditions is shown to have a similar origin as defects created with uniform stress conditions using Fowler–Nordheim tunneling, direct tunneling, or substrate-hot-electron injection. For all stressing modes, defect generation is related to the electron energy delivered to the appropriate silicon region near its interface with the thin-gate-oxide layer. A few of these hot electrons release a mobile species (believed to be hydrogen related) which can move hundreds of nm away from any positively biased contacts creating defects along its path in both silicon and oxide layers of the device. Channel-hot-electron degradation due to defect buildup along the channel is studied here as a function of stressing conditions, channel length, gate oxide thickness, and oxide processing. Procedures for predicting circuit failure under any operating conditions for logic and memory chips due to the total buildup of these defects are discussed.