1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Charge trapping in metal-ferroelectric-insulator-semiconductor structure with stack
Rent:
Rent this article for
USD
10.1063/1.1766085
/content/aip/journal/jap/96/3/10.1063/1.1766085
http://aip.metastore.ingenta.com/content/aip/journal/jap/96/3/10.1063/1.1766085
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

X-ray diffraction patterns of films after crystallization annealing. The is polycrystalline with the phases of and prominently displayed.

Image of FIG. 2.
FIG. 2.

Setup of the pulsed measurement.

Image of FIG. 3.
FIG. 3.

(a) curves of capacitor with gate. The curve shifts to right after negative bias due to polarization. The inset shows the leakage current of the gate stack between and . The leakage is less than in this range; (b) curves of the same capacitor. The curve shifts to left after negative bias.

Image of FIG. 4.
FIG. 4.

with different pulse edge slopes. The hysteresis magnitude decreases with the reduction of pulse edge slope, and is nearly on a straight line in a log-linear scale. (a) curves at different pulse edge slopes; (b) at as a function of pulse edge slope.

Image of FIG. 5.
FIG. 5.

Diagram of electron trapping and detrapping during . The gate voltage is swept from accumulation (a) to inversion (c) and then swept back to accumulation (f). In the gate stack, there were less negative charge at flat-band condition (e) than flat-band condition (b) due to the slow response of electron trapping detrapping.

Image of FIG. 6.
FIG. 6.

Pulsed curves under different pulse width while the pulse edge is kept as . There is nearly no difference in the hysteresis magnitude while the pulse width increases from to . As a result, the electron detrapping process is fast under negative bias.

Image of FIG. 7.
FIG. 7.

and pulse of capacitors with and gate. Both and show same hysteresis direction on the stack. There is no hysteresis in or on stack. (a) ; (b) .

Image of FIG. 8.
FIG. 8.

Calculated in and the normalized difference between and in stack. The is set at two values, and , respectively. Increase the remnant polarization with the decrease of trap density is the ideal method to reduce the effect of electron trapping-detrapping delay.

Image of FIG. 9.
FIG. 9.

at is plotted as a function of scan range in the capacitors with and stacks. The first increase with scan range due to the electric field increase in the layer. After reaches the maximum value, it starts to decrease due to the hole injection under high field.

Image of FIG. 10.
FIG. 10.

The normalized at (memory windows) and the shift of center [the change of at ] as a function of stress pulse number. The memory window decreases fast. The center shifts to positive direction due to the electron trapping during stress.

Loading

Article metrics loading...

/content/aip/journal/jap/96/3/10.1063/1.1766085
2004-07-26
2014-04-18
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Charge trapping in metal-ferroelectric-insulator-semiconductor structure with SrBi2Ta2O9∕Al2O3∕SiO2 stack
http://aip.metastore.ingenta.com/content/aip/journal/jap/96/3/10.1063/1.1766085
10.1063/1.1766085
SEARCH_EXPAND_ITEM