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Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits
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10.1063/1.1778485
/content/aip/journal/jap/96/9/10.1063/1.1778485
http://aip.metastore.ingenta.com/content/aip/journal/jap/96/9/10.1063/1.1778485

Figures

Image of FIG. 1.
FIG. 1.

Structure of the DG-MOSFET. Current flow is along the direction and the confinement potential varies in the direction.

Image of FIG. 2.
FIG. 2.

Saturation transconductance vs gate voltage for the scaled down DG-MOSFET. Note that the weak inversion region goes directly into the velocity saturation region. This is a common trend in ultrashort channel MOSFETs.

Image of FIG. 3.
FIG. 3.

Saturation transconductance vs low field mobility (solid line). In dotted line the drift-diffusion limited transconductance is shown (no velocity overshoot). A saturation velocity has been assumed. The absolute upper bound for the transconductance is fixed by the thermal injection velocity (dashed line). In between, very high transconductance is reported due to velocity overshoot phenomena.

Image of FIG. 4.
FIG. 4.

(a) Proximity of the saturation transconductance to the ballistic limit and reflection coefficient vs gate voltage. (b) Conduction subband edge vs position for the scaled down DG-MOSFET (high gate and drain bias). Note that the critical length is reduced relative to the mean free path , lowering the reflection coefficient near the ballistic limit .

Image of FIG. 5.
FIG. 5.

Transconductance efficiency vs current in the ballistic regime. As the channel length is scaled down, the transconductance efficiency is degraded. In the weak inversion region, the bipolar limit is approached for the DG-MOSFETs due to its near ideal subthreshold slope.

Image of FIG. 6.
FIG. 6.

Temperature effects on the transconductance efficiency.

Image of FIG. 7.
FIG. 7.

Output characteristics of the DG-MOSFET for different low field mobilities. The ballistic limit is shown for comparison.

Image of FIG. 8.
FIG. 8.

Output conductance vs drain voltage: (a) for a transistor considering several mobilities; (b) for different channel lengths in the ballistic limit.

Image of FIG. 9.
FIG. 9.

(a) Early voltage vs drain voltage for a transistor considering several mobilities. The Early voltage is enhanced with electron mobility due to the increasing current; the output conductance in the saturation region is nearly constant [see Fig. 8(a)]; (b) Early voltage for different channel lengths in the ballistic limit.

Tables

Generic image for table
Table I.

Relevant digital parameters for a set of DG-MOSFETs with metallurgical gate lengths between 10 and . Values are specified for temperatures of (left values) and maximum operation temperature of (right values). The ITRS-2001 specifications for the off-state and on-state current are shown (in parentheses) as a reference.

Generic image for table
Table II.

Intrinsic gain and cutoff frequency for the DG-MOSFET near the ultimate scaling limits. A low field mobility of has been assumed for calculations. The ITRS-2001 specifications for radiofrequency applications are shown in parentheses for comparison.

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/content/aip/journal/jap/96/9/10.1063/1.1778485
2004-10-28
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits
http://aip.metastore.ingenta.com/content/aip/journal/jap/96/9/10.1063/1.1778485
10.1063/1.1778485
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