Schematic diagram illustrating the basic function of a latch—to transform between the switch (memory) and voltage (logic) representations for a data value. The logic line is connected to two control lines with voltages and representing logical 0 and logical 1, respectively. When switch is closed and is open, the line voltage is pulled up to and thus has a logical value of 1. When switch is open and is closed, the line voltage is pulled down to and thus has a logical value of 0.
(Color) (a) (left) A schematic diagram of a crossbar latch. is the signal line, and and are the two control lines. The bistable electronic switches and connecting the two control lines to the signal line have antiparallel polarity in terms of the sign of the voltage pulses that open or close the switches. (Right) Wiring two parallel polarity switches into the antiparallel latch circuit configuration, and adding an enable switch . (b) Experimental current-voltage characteristics for two metal/molecule/metal bistable switches that were used to construct a latch. Arrows indicate hysteresis direction. Devices of area and . (c) Schematic illustration of the system voltage ranges for logic (0, 1) and switching (open switch, close switch), and the consequent control voltages (arrows) required to unconditionally and conditionally open and close the switches. Control voltages depend on the switch polarity (labeled at left , ) and the input logic state (0, 1).
(Color) Experimental demonstration of a working crossbar latch. (a) The pulse sequence on the two control lines and to achieve the latch function. Initial, interim, and final test pulses (unnecessary in actual operation) are labeled , , and . Unconditional opens, , on and are followed by conditional closes, , on and , according to the switch polarities illustrated in Fig. 2. These control pulses are in duration (followed by additional test pulses to verify switching). The final step is to restore and invert to . (b) Schematic state of the switches during each period of the pulse sequence, and switch resistances , during this pulse sequence, for an input voltage of (trial d of Fig. 4). (c) Currents (absolute value) through the switches and during this pulse sequence. The change of state during the open operation on and the close operation on are both visible (arrows).
Six trials run using the fixed pulse protocol of Fig. 3, varying only the input signal voltage. Input voltages and latched and inverted correctly with signal restoration to ; input voltages failed to latch.
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