(a) curves showing the effect of gate stack RTA time at 400 °C in ; the dots represent measured data and the lines modeled fits. (b) Corresponding plot of EOT (nm) and gate leakage at for the same devices. Dielectric reactions are evident from the changing stack EOT and with RTA time. Capacitors are , measured at 1 MHz.
TEM cross sections showing (a) as-deposited gate stack and after reaction anneal of gate stacks at 400 °C in for (b) 10, (c) 20, and (d) 40 s. The amorphous dielectric thickness is indicated in each image.
HAADF images and corresponding La , 5-edge intensity (counts increasing to the right) measured from background-subtracted EELS spectra, with position indicated as distance away from the Si interface (taken as zero). The figures show gate stacks (a) as-deposited, (b) after a 20-s RTA, and (c) after a 40-s RTA in .
MEIS spectrum of a stack after an in situ reaction anneal at 500 °C for 10 min in . A MEIS simulation (solid line) fit to the data indicates a single silicate layer of 12A and no detectable at the interface.
(a) curves and (b) gate leakage of in situ reaction annealed MOS devices having EOT values of 0.49 and 0.63 nm, and corresponding leakage at of and , respectively. The dots represent the measured data, while the lines in (a) are fits using the CVC model. Capacitor size is , using a 1-MHz measurement frequency.
Effects of a 400 °C, 20-min forming gas anneal on a lanthanum silicate dielectric stack; the data points show positive and negative sweeps, the line a modeled fit (EOT 0.89 nm) to the data. The flatband voltage has shifted 0.23 V closer to the expected value (a reduction in positive charge density), and the “hump” related to the interface traps has been reduced. Capacitors are , measured at 1 MHz.
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