Schematic diagram of the device geometry. The quantum wire (marked QW) is located at the bottom of the V-shaped groove. The inset shows a cross-sectional TEM image of the wire, on which the charge distribution is schematically depicted.
Wire preparation by cleaved edge overgrowth of GaAs–AlGaAs by molecular-beam epitaxy (courtesy of Amir Yacoby79).
(a) Differential conductance of a long wire in a quantum well versus top-gate voltage . The different curves correspond to different temperatures. Inset: The differential conductance versus temperature for a value of marked by the arrow; (b) Conductance versus gate voltage for gate width at various temperatures, after subtraction of a series resistance.
Conductance values of the first plateau versus temperature in the wire. Both theoretical expressions are plotted for the same parameter of .
(a) AFM image of a carbon nanotube on top of a substrate with two thick Pt electrodes; (b) AFM image of a completed device. The bright regions are the lithographically defined metallic contacts, labeled 1 to 4. A nanotube rope is clearly visible as a brighter stripe underneath the metallic contacts (courtesy of Cees Dekker95 and Paul McEuen96).
Conductance plotted versus temperature for individual nanotube ropes. (a) Data for ropes that are deposited over pre-defined leads (bulk-contacted); (b) data for ropes that are contacted by evaporating the leads on top of the ropes (end-contacted). The plots show both the raw data (solid line) and the data corrected for the temperature dependence expected from the Coulomb blockade model (dashed line). The upper inset to (a) shows the power law exponents inferred for a variety of samples. Open circles denote end contacted samples, and crosses denote bulk-contacted ones (courtesy of Paul McEuen88).
The differential conductance measured at various temperatures. Inset in (a): curves taken on a bulk-contacted rope at temperatures , K: 1.5, 8, 20 and 35. Inset in (b): curves taken on an end-contacted rope at temperatures , K: 20, 40 and 67. In both insets, a straight line on the log-log plot is shown as a guide to the eye to indicate power-law behavior (courtesy of Paul McEuen88).
Linear-response two-probe conductances of segments I and II and across the metal-metal junction of plotted against temperature on a double-logarithmic scale. The data are fitted (solid lines) by the power law, , which is associated with the suppression of tunneling density of states in a Luttinger liquid. The exponents for the two straight segments are 0.34 and 0.35, respectively. The fit is particularly convincing for the data across the kink. An exponent of 2.2 is obtained, which is consistent with end-to-end tunneling between two Luttinger liquids (courtesy of Cees Dekker89).
(a) Top view layout of the wire and its contacting scheme. The sample is fabricated using the CEO method. The 1D wire (thick black line) exists along the cleaved surface and overlaps a 2DEG over the entire edge. The metallic gate depletes the 2DEG over a wide segment, thereby, forming an isolated 1D wire that is coupled at its ends to the overlapping 2DEG. A further increase in the top gate voltage reduces the wire density continuously to depletion. (b) Conductance of the wire as a function of the top gate voltage. Inset: A zoom-in of the conductance of the wire in the sub-threshold region (courtesy of Ophir Auslaender and Amir Yacoby82).
Fabrication of a room-temperature single-electron transistor within an individual metallic carbon nanotube by manipulation with an AFM. (a) Nanotube between Au electrodes on top of a substrate with a gate-independent resistance of . (b) Nanotube after creation of a buckle. The dragging action has resulted in a tube that is bent so strongly that it has buckled. A second dragging action is performed as indicated by the arrow. (c) Double-buckle nanotube device. (d) Enlarged image of the double-buckle device (courtesy of Cees Dekker9).
Power-law temperature dependence of the conductance, demonstrating correlated sequential tunneling through the nanotube SET device. Lower data (right-hand scale) show the peak height for the conductance, following a power-law function with exponent 0.68. The conductance integrated over the gate voltage range, (left-hand scale), also follows a power-law function with exponent 1.66. The inset shows the peak width versus , which displays a linear behavior (courtesy of Cees Dekker9).
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