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Ethernet based list processing controller for high speed data acquisition systems
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10.1063/1.2338300
/content/aip/journal/rsi/77/9/10.1063/1.2338300
http://aip.metastore.ingenta.com/content/aip/journal/rsi/77/9/10.1063/1.2338300

Figures

Image of FIG. 1.
FIG. 1.

Functional block diagram of the LPCC.

Image of FIG. 2.
FIG. 2.

Data throughput kbytes/s and event rates/s.

Image of FIG. 3.
FIG. 3.

Event rates acquired by the LPCC with hit-pattern based processing.

Image of FIG. 4.
FIG. 4.

LP cycle activated on LAM(L) with simultaneous reads (RD).

Tables

Generic image for table
Table I.

LP commands (Station No. 30).

Generic image for table
Table II.

Control and status register. (R) denotes read only, (W) write only, and (−) do not care.

Generic image for table
Table III.

Mode control value. “R” denotes read only, “W” write only, and “RW” read and write.

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/content/aip/journal/rsi/77/9/10.1063/1.2338300
2006-09-08
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Ethernet based list processing controller for high speed data acquisition systems
http://aip.metastore.ingenta.com/content/aip/journal/rsi/77/9/10.1063/1.2338300
10.1063/1.2338300
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