(a) Block diagram of a basic feedback control system. Here G(ω) and H(ω) are the transfer functions of the plant and controller respectively, with X(ω) being the input noise and Y(ω) being the output of the system (i.e., error signal). Also shown is the placement of a network analyzer, with X′(ω) being the extra noise added to the system in the form of a swept sine wave (Sine) or white noise (WN). (b) Bode plot of the transfer function of a code-cleaner cavity for (i) a network analyzer (model MS4630B from Anritsu) and (ii) a white noise generator included in the code.
(a) Depiction of the physical system and hardware required for digital locking using the code presented here, in this case for a bow-tie OPO cavity doubly resonant with a green (532 nm - dashed line) and a red (1064 nm - solid line) field, the latter being used to lock the cavity position on reflection. MSPS – M samples s−1; PXI – PXI chassis; FPGA – field programmable gate array card; Freq. Gen. – frequency generator; RT – real time controller; AIP – analog input to FPGA (sampling frequency < 1 MSPS); AOP – analog output from FPGA (sampling frequency < 1 MSPS); HS ADC – high speed analog to digital converter (80 MSPS); D – detector; Clock Gen. – digital clock generation board; fmod – modulation frequency for lock; EOM – electro-optic modulator; PZT – piezo-electric transducer; PPKTP – periodically poled potassium titanyl phosphate crystal; HV Amp – high voltage amplifier; and Expt. – rest of experiment. Inset shows the different signals which are used for locking (DC – dc reflection signal; ES – Error signal; Scan – scan function) as a function of PZT position. (b) Depiction of LabVIEW® code used to program FPGA cards. CIC – cascaded-integrator-comb filter; PII controller – proportional, integral, double integral controller; Scan T – scan threshold; Lock T – lock threshold; T – true; F– false.
(a) Magnitude plot of system transfer function for an OPO cavity with controller gain increasing from (i) to (iv). (b) Normalised rms values for these traces for both the error and dc signals. Error bars show standard deviation across 10 runs used for each point. Also shown is the sequence in which the different gains are added, the bandwidth of the system (ω B ) and phase margin (PM) measured by the code.
(a) Error signal, measured in MHz, and (b) dc signal, normalized to total peak height, for (i) a digital PII and (ii) analog PI controller, measured over a 1 h period. (c) The digital PII controller signal measured during the digital run showing the frequency drift of the laser which was compensated for. (d) Magnitude plots of the system transfer function for (i) no locking, (ii) for locking with the analog PI controller, and (iii) for locking with the digital PII controller.
(a) Experimental setup. MC – mode cleaner (R – red, G – green); BT – bow-tie cavitiy; PZT – piezo-transducer phase lock; HOM – homodyne lock (T – tomographic, x 2 – double homodyne); AmM – amplitude modulator; PhM – phase modulator; Sh – mechanical shutter; SQZ data – squeezing data; D – lock dependencies (0 = no dependencies); F – FPGA lock is controlled from; Ext. Demod. – external demodulation carried out for these locks to produce the error signal; AIP – analog input; DAQ – data acquisition card; Clk. Sig. – clock signal; and LO – local oscillator. (b) Flow diagram of data acquisition procedure used to take squeezing data (SQZ) for various angles of the tomographic lock ϕ, as well as take dark noise (DN) and shot noise (SN) traces. Values for the number of experimental runs N, number of squeezing traces for each tomographic angle M, and change in tomographic lock angle between runs Δϕ are defined by the user. (c) Plot of variance in noise normalised to the quantum noise limit (QNL), as a function of tomographic lock angle taken using the above procedure with a total of 1.2 million points per angle, and Δϕ = π/36. Circles: data points; dashed line: theoretical fit.
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