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A digital optical phase-locked loop for diode lasers based on field programmable gate array
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10.1063/1.4750143
/content/aip/journal/rsi/83/9/10.1063/1.4750143
http://aip.metastore.ingenta.com/content/aip/journal/rsi/83/9/10.1063/1.4750143
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Basic structure diagram of a common PLL. It is composed of PFD, loop filter, PID controller and oscillator. The first three parts formed the controlling circuit. The PID controller is optional depend on the type of PFD. Oscillator is voltage controlled oscillator or digital controlled oscillator depends whether the platform is analog or digital.

Image of FIG. 2.
FIG. 2.

The structure of OPLL in our design. Three modules in dashed box (a) formed the controlling circuit. The parts in dashed box (b) include lasers, DAC chip for fast current modulation for slave laser, optical setups for lasers’ beat note, and down shifting circuit for beat note. These parts could be regarded as an equivalent digital controlled oscillator (DCO) for PLL.

Image of FIG. 3.
FIG. 3.

The logic diagram of the controlling circuit. It is divided into three parts (a), (b), and (c) and all the three parts are implemented in a single FPGA chip. D FF: D flip-flop. &: AND logic gate. TRC: Twisted ring counter. Reg: Register. The signal line with a slash through it means signal bus with multi-bit.

Image of FIG. 4.
FIG. 4.

(a) The typical spectrum of the closed loop beat note signal (resolution/video bandwidths = 10 kHz). (b) Expanded view around the narrow beat note signal (resolution/video bandwidth = 1 Hz).

Image of FIG. 5.
FIG. 5.

Phase noise spectrum diagram of the closed loop beat note signal. The peaks at 570 kHz indicate the bandwidth of feedback control loop.

Image of FIG. 6.
FIG. 6.

(a) 8192 samples of phase error signal in 163.84 μs duration when the beat note is phase-locked. Phase error is kept in the range of ±0.5 rad. (b) Expanded view of 750 samples in duration from 43rd to 58th μs. A periodical oscillation of about 500 to 600 kHz can be seen obviously, probably due to the proportional parameter in PID is a little too high.

Image of FIG. 7.
FIG. 7.

Transition process in time domain. 8192 samples of phase error signal in 163.84 μs duration when the OPLL is locked on but the master laser is modulated by step signal. At t1, step signal has been applied, and t2 phase has been locked again. Transition time between t1 and t2 is about 100 μs under the step signal to master laser of about 10 MHz.

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/content/aip/journal/rsi/83/9/10.1063/1.4750143
2012-09-05
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: A digital optical phase-locked loop for diode lasers based on field programmable gate array
http://aip.metastore.ingenta.com/content/aip/journal/rsi/83/9/10.1063/1.4750143
10.1063/1.4750143
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