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A time digitizer for space instrumentation using a field programmable gate array
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10.1063/1.4818965
/content/aip/journal/rsi/84/8/10.1063/1.4818965
http://aip.metastore.ingenta.com/content/aip/journal/rsi/84/8/10.1063/1.4818965

Figures

Image of FIG. 1.
FIG. 1.

Time-of-Flight Space Instrument Architecture (FIPS) showing the ion path. Ions passing through the carbon foil eject electrons that are nearly instantaneously detected by the position-sensitive Start MCP (START PULSE). The particle continues on to strike the Stop MCP (STOP PULSE) and the instrument TDC function provides a measure of particle velocity. Adapted from Ref. .

Image of FIG. 2.
FIG. 2.

Delay-line architecture: Carry-chain logic is used to propagate a signal edge through the FPGA. Associated latches capture the carry-chain (delay-line) pattern of each internal clock cycle. The data pattern is then analyzed for the presence of event edges.

Image of FIG. 3.
FIG. 3.

Xilinx Virtex II CLB (configurable logic block) architecture. An array of these logic blocks with interconnecting, configurable wiring constitutes the logic fabric of this FPGA family. There are 40 of these blocks in each column of the Virtex XC2V1000 device.

Image of FIG. 4.
FIG. 4.

Delay-line element delays for 3-column Xilinx implementation. Dark line is the neural network result used in testing. A more accurate histogram-derived series is superimposed. Significant nonlinearities in delay-line stage timing are evident. The two large negative spikes correspond to a time overlap introduced between delay-line columns so that an event (edge) is propagating up the next delay-line column before running off the end of the previous column. (See Sec. V .)

Image of FIG. 5.
FIG. 5.

Xilinx multiple carry-chain columns. The pulse propagation time through a single column is too fast (<5 ns) for the system clock (100 MHz) to capture every pulse edge. To lengthen the delay-line time to between 1 and 2 clock periods, three CLB columns are used.

Image of FIG. 6.
FIG. 6.

Possible operational modes for TDC architecture. The FPGA implementation provides flexibility of operation in various architectures, without substantial changes to the overall design implementation.

Image of FIG. 7.
FIG. 7.

FPGA TDC architecture for a TOF mass-spectrometer such as FIPS, as implemented in a Xilinx Virtex II. The architecture may be adapted to any FPGA with accessible high-speed signal paths for delay-line construction.

Image of FIG. 8.
FIG. 8.

Temperature compensation eliminates error due to delay-line propagation variability; performance measured for the operational Virtex II implementation. Plotted are delay times for a fixed 45-ns delay pulse pair measured as a function of temperature.

Image of FIG. 9.
FIG. 9.

Xilinx Virtex II TDC performance. Pulse pairs from 5-ns to 2005-ns separation were applied to the FPGA in sets of 5000 to produce the statistical data.

Tables

Generic image for table
Table I.

Theoretical versus measured performance.

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/content/aip/journal/rsi/84/8/10.1063/1.4818965
2013-08-27
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: A time digitizer for space instrumentation using a field programmable gate array
http://aip.metastore.ingenta.com/content/aip/journal/rsi/84/8/10.1063/1.4818965
10.1063/1.4818965
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