HRTEM image simulations of structural defects in gate oxides
- Conference date: 26-29 June 2000
- Location: Gaithersburg, Maryland (USA)
In this study, we performed HRTEM image simulations of a MOSFET device to determine the ability of HRTEM to detect gate oxide defects. The gate oxide was modeled as an amorphous silicon oxide 16.3 Å-thick, sandwiched between a gate and substrate. Both the gate and substrate were modeled as (100) silicon viewed along the  direction. Crystalline silicon defects were embedded in the model gate oxide and simulated images were calculated using a multi-slice approach with varying defect morphology, composition, size and orientation. Simulations predict that defects should be observable for very small specimen thickness (<100 Å) and large defect sizes (>40 Å), but not for specimen thickness and defect sizes typical of advanced CMOS devices analyzed in routine laboratory electron microscopy.
- Crystal defects
- High resolution transmission electron microscopy
- Amorphous semiconductors
- Electron microscopy
- Metal insulator semiconductor structures
MOST READ THIS MONTH
MOST CITED THIS MONTH
Y. K. Semertzidis, M. Aoki, M. Auzinsh, V. Balakin, A. Bazhan, G. W. Bennett, R. M. Carey, P. Cushman, P. T. Debevec, A. Dudnikov, F. J. M. Farley, D. W. Hertzog, M. Iwasaki, K. Jungmann, D. Kawall, B. Khazin, I. B. Khriplovich, B. Kirk, Y. Kuno, D. M. Lazarus, L. B. Leipuner, V. Logashenko, K. R. Lynch, W. J. Marciano, R. McNabb, W. Meng, J. P. Miller, W. M. Morse, C. J. G. Onderwater, Y. F. Orlov, C. S. Ozben, R. Prigl, S. Rescia, B. L. Roberts, N. Shafer‐Ray, A. Silenko, E. J. Stephenson, K. Yoshimura and EDM Collaboration
Article metrics loading...