- Conference date: 5-7 June 2006
- Location: Toledo (Spain)
The Compact Optoelectronic Integrated Neural (COIN) coprocessor is a rugged, pixelated, parallel optoelectronic system that is designed to run neural network‐type algorithms in native hardware. The goal of the COIN project is to explore the potential capabilities and limitations of such systems. The optoelectronics, holographic interconnections, and VLSI circuits of the first prototype machine have been fabricated and characterized individually. Recent work on the project was focused on designing the computational components and developing hierarchal system models that can provide accurate, timely, and efficient performance estimates of the COIN coprocessor while it is still in the pre‐integration stage. In this paper, we present an overview of the project and some of the simulated results that demonstrate the potential training and learning characteristics of the system.
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