Impact of Cu/low‐k Interconnect Design on Chip Package Interaction in Flip Chip Package
- Conference date: 5–7 November 2008
- Location: Austin (Texas)
The impacts of Cu/low‐k interconnect structures and solder bump layouts on Chip Package Interaction (CPI) in Flip Chip Ball Grid Array (FCBGA) was investigated. The energy release rates (ERR) that indicate the driving force for delamination were calculated to evaluate the impact of CPI on mechanical reliability of Cu/low‐k in FCBGA. First, two metal layer interconnect structure was modeled to find the effects of the mechanical properties of inter layer dielectric (ILD) materials on ERR. The ERR was found to increase rapidly when the modulus of ILD is lower than 10 GPa. Then the number of the interconnect layer was increased to four to find the impact of wiring dimensions on CPI. The ERR at the upper interface were consistently higher than those of lower interface. However, when TEOS is used for M4 level, low‐k is used for M3 and Ultra low‐k is used for M2 and M1 level, the ERR at M3 level becomes higher than that at M4 level. The wiring dimension and mechanical properties of ILD were found to be important in controlling CPI. Then the number of interconnect layer was increased to seven and nine layers where the dimension was determined by 65 nm technology rule. The ERR increased with increasing the crack length which indicates that the crack will keep growing when it generates. Finally, arranging the dummy bump was found to be effective to reduce the peeling stress at outermost bump. Then, the impact of interconnect design and material properties of ILD on CPI will be discussed.
- Flip chip
- Materials properties
- Mechanical properties
- Dielectric materials
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