Fast Arithmetic Using Signed Digit Numbers and Ternary Logic
- Conference date: 14–16 January 2009
- Location: Agra (India)
Redundant Binary Signed Digit Number System may not be convenient for manual computations but may be useful in designing high‐speed arithmetic machines. This number system is gaining popularity in computationally intensive environments particularly due to possessing of the carry‐free addition/subtraction properties. This property has enabled arithmetic operations such as addition, multiplication, division, square root, etc., to be performed much faster than with conventional binary number systems. In RBSD number system carry propagation chains are eliminated which reduces the computational time substantially, thus enhancing the speed of the machine. The credit of RBSD number system goes to Robertson, who proposed it in 1959 and Avizienis in 1961.
In this paper, some of the recent contributions in the area of design of redundant arithmetic based addition and multiplication algorithms and architectures are briefly discussed. Also use of parallel implementation for architectures is discussed so that the enhancement in speed through the use of redundant arithmetic is possible. Also, in this paper, RBSD adder is designed. After calculation and comparison it is concluded that efficiency of RBSD adder is much better than the other adders. An addition of two’s complement circuit will make an RBSD subtractor. These Adders/Subtractors can further be used as building blocks for fast multiplication, division and square root operation.
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