New switches are being designed based on carrier spin, excitons, and other properties. Graphene is considered a strong candidate for many of these applications. New phenomena abound at nanoscale dimensions, and graphene is no exception. Quantum confinement impacts materials properties and measurement itself. Berry Phase corrections to carrier transport measurements are widely recognized. New materials such as graphene are difficult to find, manipulate, and measure. One key question is the number of graphene layers in a sample and the stacking of multilayer samples. Multiple characterization methods are necessary including transmission electron microscopy (TEM), Low Energy Electron Microscopy (LEEM), nano‐Raman, and several scanned probe methods. Multislice simulations are a useful guide in determining TEM capability and imaging conditions. Initial simulation work points to the ability to distinguish stacking patterns. Recent work indicates that LEEM can determine the number of layers and the morphology of a graphene sample. Raman provides an excellent means of determining the number of layers in a stack of graphene. Single electron transistors have mapped electron‐hole puddles across a sample area. Quantum confinement and Berry Phase corrections are two examples of quantum phenomena that alter the properties of nano‐scale structures. Optical and electrical properties must be understood before they are measured. This paper will cover the research and development of metrology for CMOS Extension and Beyond CMOS using graphene as an example.
- Low energy electron microscopy
- Materials properties
- Transmission electron microscopy
- Electrical properties
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