- Conference date: 29 June–1 July 2009
- Location: Kuala Lumpur (Malaysia)
The readout control of the former ZEUS detector comprises of five analogue modules, i.e. table control, pipeline control, buffer control, format control and generator module. A new readout control in form of Programmable Gate Array (FPGA) module, was designed by integration the five analogue modules into a single module. This paper discusses the design of the readout FPGA‐based readout control and its simulation on Quartus II.
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