- Conference date: 25–29 June 2012
- Location: Valladolid, Spain
Reduction of polysilicon sheet resistivity and polysilicon depletion ratio (PDR) are two major challenges for improving the memory cell characteristics of sub-20 nm NAND Flash devices. High phosphorus doses are implanted into in situ doped polysilicon floating gates to improve PDR, but phosphorus concentrations that are too high can degrade cell characteristics by increasing trapped charge in the TNOX(Tunnel Oxide). It is also important to prevent the bending of narrow polysilicon lines during floating gate implantation. We explored various conditions of low energy, high tilt phosphorus implants for floating gate doping using a spot beam high current implanter. The optimal concentration of implant energy, tilt angle, and thermal annealing has been shown to improve PDR and floating gate TOP CD control.
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