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Stress and electromigration modelling for confined chip level interconnect lines
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10.1063/1.54651
/content/aip/proceeding/aipcp/10.1063/1.54651
http://aip.metastore.ingenta.com/content/aip/proceeding/aipcp/10.1063/1.54651
/content/aip/proceeding/aipcp/10.1063/1.54651
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/content/aip/proceeding/aipcp/10.1063/1.54651
1998-01-05
2015-07-28
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229c8a00d8fe88cf152414eb5d9cd803 conferences.conference_paperzxybnytfddd
Scitation: Stress and electromigration modelling for confined chip level interconnect lines
http://aip.metastore.ingenta.com/content/aip/proceeding/aipcp/10.1063/1.54651
10.1063/1.54651
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