- Conference date: 23-27 March 1998
- Location: Gaithersburg, Maryland (USA)
The reliability of gate oxides is becoming a critical concern as oxide thickness is scaled below 4 nm in advanced CMOS technologies. Traditional reliability characterization techniques must be modified for very thin gate oxides that exhibit excessive tunneling currents and soft breakdown. As intrinsic reliability limits are approached by increasing chip temperature and electric fields, it becomes essential to fully understand the physical mechanism(s) responsible for gate oxide wear-out and eventual breakdown. Issues relating to the reliability testing of ultra-thin oxides are discussed with examples.
- Dielectric thin films
- Electric currents
- Electric fields
- Electrical breakdown
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