- Conference date: 23-27 March 1998
- Location: Gaithersburg, Maryland (USA)
Doping requirements for CMOS devices have been defined out to 50 nm gate size devices  and provide a context for the evaluation of in-line characterization needs. The wide range of doping processes used in CMOS fabrication, ranging in energies from ⩽1 keV to over 1 MeV and in dose from to presents a significant challenge to provide adequate coverage in a high-accuracy, fast-response metrology. An added challenge is to provide characterization tools that function in-line with fab operations or, even better in-situ with the process chamber. Fortunately, a wide variety of materials characterization techniques have been adapted to the needs of doping technology processes . However, the rapid advance of IC process requirements, a fundamental characteristic of the IC business, has pushed most of these techniques to their limits of performance. The list of critical areas for in-line monitoring starts with improved dosimetry for both shallow (source/drain and channel doping) and deep (CMOS well) junctions. Added to the dosimetry requirements is an increased need to monitor dopant profile shape and junction depth, especially for shallow junction’s . Monitoring of elemental and particulate contamination levels is critical for adequate yield and cost-effective operations. Because the ion ranges for ultra-shallow junctions are ⩽10 nm and the smallest particle size that can be imaged with routine techniques is ⩾180 nm, new technology is required to detect small size “killer particles” that can mask low-energy (⩽1 keV) ion beams. Control of wafer charging for gate dielectrics shrinking below 5 nm and increased antenna factors for large-area logic chips will drive the need for increased monitoring of net current flow from the ion beam-charge control plasma leading to development of in-situ sensing of plasma j-V characteristics.
- Metal insulator semiconductor structures
- Charged currents
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