- Conference date: 23-27 March 1998
- Location: Gaithersburg, Maryland (USA)
Some shortcomings of the standard MOS device models and algorithms used for parametric characterization of the device in deep sub-micron technologies are discussed. These include field and channel length dependent mobility, un-pinned surface potential due to operation in weak inversion, Poly-depletion, quantum mechanical (QM) effects, and carrier velocity saturation. Enhancements to the basic model are proposed to account for these higher order effects to improve the accuracy of extracted parameters. Issues and challenges for evaluation of gate oxide parameters are also discussed. The effect of direct tunneling induced gate leakage is the most significant hurdle to overcome there. This leakage impacts many characterization methods as well as reliability evaluation methodologies. Scaling related issues in interconnect evaluation are also discussed. There, the main issues are in coping with narrow, high aspect ratio lines and spaces with varying thickness due to CMP.
- Metal insulator semiconductor structures
- Carrier mobility
- Quantum effects
- Surface charge
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