A noise simulation post-processor: A new tool for low noise device design
- Conference date: 7-8 Aug 1998
- Location: St. Louis, Missouri (USA)
The development of a numerical, postprocessor, device noise simulator, capable of simulating velocity fluctuation and Hooge type 1/f noise is described. Three-dimensional noise maps are presented for a bipolar transistor and MOSFET revealing the noise contributions of specific device areas. Where applicable, good agreement with analytical results is obtained.
MOST READ THIS MONTH
MOST CITED THIS MONTH
Article metrics loading...