ION IMPLANTATION TECHNOLOGY 2101: 18th International Conference on Ion Implantation Technology IIT 2010
1321(2011); http://dx.doi.org/10.1063/1.3548348View Description Hide Description
In the series of Ion Implantation Technology conferences, several excellent reviews of the history of ion beam technology development have been presented. All of these articles have included descriptions of the evolution of ion implantation equipment and processing. Since 1970, a wide range of other ion beam processing techniques has been developed, not only ion implantation into semiconductor materials for IC fabrication, but also many other techniques for electronic, magnetic and optical devices. In this paper, several of Japan’s important contributions to ion beam technologies and development efforts involving international collaborations in these fields will be discussed.
1321(2011); http://dx.doi.org/10.1063/1.3548476View Description Hide Description
Industrial aspects of the evolution of ion implantation technology will be reviewed, and their impact on the semiconductor industry will be discussed. The main topics will be the technology’s application to the most advanced, ultra scaled CMOS, and to power devices, as well as productivity improvements in implantation technology. Technological insights into future developments in ion‐related technologies for emerging industries will also be presented.
FinFET Doping; Material Science, Metrology, and Process Modeling Studies for Optimized Device Performance1321(2011); http://dx.doi.org/10.1063/1.3548341View Description Hide Description
In this review paper the challenges that face doping optimization in 3‐dimensional (3D) thin‐body silicon devices will be discussed, within the context of material science studies, metrology methodologies, process modeling insight, ultimately leading to optimized device performance. The focus will be on ion implantation at the method to introduce the dopants to the target material.
1321(2011); http://dx.doi.org/10.1063/1.3548360View Description Hide Description
This paper presents a novel strategy to achieve conformal FINFET extension doping with low tilt‐angle beam‐line ion implantation. The process relies on the self‐aligned cap layer formation exclusively on top of the FIN to tune doping levels in this particular area by partial dopant trapping. The conformality itself is evaluated for n‐ and p‐type dopants by a novel extraction method applied to FIN resistor test structures. Furthermore, the process was integrated into a full NMOS device flow and compared to a highly tilted and more conformal As implant condition.
Plasma Implantation Technology for Upcoming Ultra Shallow and Highly Doped Fully Depleted Silicon On Insulator Transistors1321(2011); http://dx.doi.org/10.1063/1.3548380View Description Hide Description
To face the continuous dimensions downscaling for upcoming semiconductor devices, we have investigated a plasma immersion ion implantation way and have compared the results to a conventional one. This new implantation method allows, in particular, high and thin doping concentration to field source and drain requirements for 32 nm node and below. In addition to this key step, a silicon selective epitaxy growth has been performed.
Thus, n‐type and p‐type ion implantations have been carried out on thin blanket SOI substrates in Pulsion® plasma ion implantation tool manufactured by Ion Beam Services, with or precursors. Then a recrystallization annealing followed by silicon selective epitaxial growth has been performed in a reduced pressure chemical vapor deposition tool.
Regarding n‐type implantation we observed a poly‐silicon growth in areas where the top silicon has been amorphous down to the buried oxide and a mono‐silicon growth for areas where the top silicon has not been completely amorphous. Indeed, in this case recrystallization annealing was not sufficient to allow lengthwise solid phase epitaxy growth whereas there were no difficulties for axial one.
Regarding p‐type implantations no epitaxial growths have been observed at all. This lack of growth cannot be explained by a complete silicon amorphization which would have led to a growth of poly‐silicon like for n‐type implantation. According to our first results this growth vacancy could be explained by the very high boron atoms concentration on the substrate surface. The latter being resistant to HF‐last cleaning could thus block silicon nucleation.
However some rinsing processes, more or less aggressive, have been tested to remove this boron silicon alloy layer. Among these different tests, hydrochloric or plasma etching have provided, in some specific cases, promising results allowing an epitaxial silicon growth.
1321(2011); http://dx.doi.org/10.1063/1.3548397View Description Hide Description
The consumer appetite for a rich multimedia experience drives technology development for mobile hand‐held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi‐dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI’s core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.
1321(2011); http://dx.doi.org/10.1063/1.3548426View Description Hide Description
To extend current process, it is required develop new implantation method. One of promising candidates are carbon implant, cold implant, or cold carbon implantation. To improve transistor properties, we have evaluated those implantation methods in Lightly doped drain (LDD), Source/Drain(S/D,P+ BF2, N+ As) and N+ add implant step. Carbon (C+) implantation could improve Short channel effect(SCE), cold implantation decrease Drain induced barrier lowering(DIBL), Sense and amplifer(S/A) mismatch and contact resistance. Cold carbon implant improved junction Breakdown voltage(BV). Optimization of process conditions and junction profiles is required for optimum device performance.
Improvement of Poly Profile in Sub 30 nm Device By Damage Engineering and Tilted Implantation Method1321(2011); http://dx.doi.org/10.1063/1.3548439View Description Hide Description
Conventionally, out‐gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this out gassing causes degradation of PDR and cell characteristics in sub‐30 nm device. Usually, there is a method to keep PDR of in‐situ doped poly‐Si by increasing the concentration of but this method also causes cell characteristics degradation by trap charge of tunnel oxide.
So, we used another method of ion implantation to control out‐gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation.
Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.
1321(2011); http://dx.doi.org/10.1063/1.3548450View Description Hide Description
Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K/metal gate or stress induced carrier mobility enhancement. Ultra‐Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra‐Shallow Junction formations in terms of figure of merits of Rs/Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, ) molecular implant and Phosphorus along with co‐implantation and PTC II (VSEA Process Temperature Control) technology, sub‐32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state‐of‐the‐art 28 nm device manufacturing.
Process Characterization Of Low Temperature Ion Implantation Using Ribbon Beam And Spot Beam On The AIBT iPulsar High Current1321(2011); http://dx.doi.org/10.1063/1.3548462View Description Hide Description
The damage and amorphous layer formation properties of a 6 keV carbon implant were investigated using spot beam and ribbon beam and substrate temperature. The effects of wafer temperature on dopant activation and diffusion were further investigated for boron implants between 300 eV and 2 keV and arsenic implants between 2 keV and 20 keV. The carbon implant amorphization characteristics can be understood using the concept of critical dose for amorphization. B and As activation was found to be 15%–20% improved at the lowest implant temperature but with similar junction depths compared to higher implant temperatures. Higher energy implants showed less or no activation or junction depth improvement at lower implant temperatures.
1321(2011); http://dx.doi.org/10.1063/1.3548464View Description Hide Description
Wafer temperature during implant has a dominate effect on the amorphous layer thickness and post anneal residual defects which can result in difference in device performance and difficulties in tool matching between different implant systems, namely batch type vs. single wafer implanter and spot beam vs. ribbon beam system. Although the implant temperature set point can be well defined and controlled, the instantaneous temperature on wafer during implant is quite complicated interactions among beam shape, dose rate, duty cycle and cooling system to the behavior of defect generation and dynamic annealing. A batch system, iStar, and a single wafer system, iPulsar, which delivers both spot beam and ribbon beam with cold implant capability were used to study the effect of implant temperature to the post anneal residual defects by 15 keV implant after 850 °C/30s anneal. Measurements from Rs, SIMS, plane view TEM are compared and analyzed. The results by ribbon beam and spot beam are also compared.
1321(2011); http://dx.doi.org/10.1063/1.3548465View Description Hide Description
As DRAM devices scale below the 30 nm node, the device performance requirements for the input/output CMOS circuits are increasing significantly. Specifically, short channel effects (SCE) and their associated leakage currents are becoming increasingly problematic. Various forms of implant damage engineering are being investigated to minimize leakage from SCE. These include changes to the implanter architecture (spot vs. ribbon beam), implantation temperature, and implant species (monomer vs. molecular). We studied the defect morphology both after ion implantation and after annealing for the PMOS S/D implant on an advanced DRAM device. The implants were combinations of C, and Implant temperatures ranged from to Thermawave, SIMS, Rs and TEM were used to characterize the samples.
Integration of High Dose Boron Implants—Modification of Device Parametrics through Implant Temperature Control1321(2011); http://dx.doi.org/10.1063/1.3548466View Description Hide Description
In the present study, we have extended a previously reported 250 nm logic p‐S/D implant (7 keV B ) process matching exercise  to include wafer temperature, and demonstrate that matching can be obtained by increasing the temperature of the wafer during implant. We found that the high dose rate delivered by the single wafer implanter caused the formation of a clear amorphous layer, which upon subsequent annealing altered the diffusion, activation, and clustering properties of the boron. Furthermore, increasing the temperature of the wafer during the implant was sufficient to suppress amorphization, allowing profiles and device parameters to become matched. Figure 5 shows a representative set of curves indicating the cluster phenomena observed for the lower temperature, high flux single wafer implanter, and the influence of wafer temperature on the profiles. The results indicate the strong primary effect of dose rate in determining final electrical properties of devices, and successful implementation of damage engineering using wafer temperature control.
1321(2011); http://dx.doi.org/10.1063/1.3548467View Description Hide Description
As CMOS devices continue to shrink, the formation of ultra shallow junction (USJ) in the source/drain extension remains to be a key challenge requiring high dopant activation, shallow dopant profile and abrupt junctions. The next generations of sub nano‐CMOS devices impose a new set of challenges such as elimination of residual defects resulting in higher leakage, difficulty to control lateral diffusion, junction stability post anneal and junction formation in new materials. To address these challenges for advanced technological nodes beyond 32 nm, it is imperative to explore novel species and techniques. Molecular species such as Carborane a novel doping species and a promising alternative to monomer Boron is of considerable interest due to the performance boost for 22 nm low power and high performance devices. Also, to reduce residual defects, damage engineering methodologies have generated a lot of attention as it has demonstrated significant benefits in device performance. Varian proprietary techniques to perform implants at cold temperatures (PTC II) have demonstrated lower junction leakage, enhanced activation, reduced dopant diffusion and less dopant deactivation due to the reduction of self‐interstitial atoms present at the end‐of‐range (EOR) with low implant temperatures. In this paper, for the first time, there is a comprehensive study of the effect of implant temperature on defect engineering affecting deactivation/reactivation, and it is well established in this paper that colder the implant temperature the better it is for damage engineering with reduced EOR defects and better amorphization. The effect has been studied over a wide range of implant temperature. To understand any difference in deactivation between molecular and monomer Boron and to provide direct comparison equivalent Boron implants, co‐implanted with Carbon were also studied. Implants with wide range of temperatures are implemented using PTC II. This paper will also show how damage reduction correlates with optimum junction formation and stability.
1321(2011); http://dx.doi.org/10.1063/1.3548468View Description Hide Description
This paper reports on the ultra‐rapid thermal annealing of next generation MOSFETs. In ultra‐rapid thermal annealing, the most important issue is to achieve a good balance between electrical activation and impurity diffusion. Another issue of annealing implantation damages is also discussed: Optimized annealing combined with millisecond annealing and conventional halogen lamp annealing is necessary for annealing out defects at end‐of range region. Application possibilities of millisecond annealing for deep junction activation and oxidation are also discussed.
1321(2011); http://dx.doi.org/10.1063/1.3548469View Description Hide Description
We have investigated the effects of FLA technique on the DRAM peripheral transistor improvements by integrating into the SDRTA (Source/Drain RTA) and ADD RTA (Add RTA after contact formation). FLA with conventional RTA was not effective because of SCE (Short Channel Effect) control. FLA only was effective to improve SCE and Iop, and especially more effective on technology shrink. By flash anneal (FLA), we tried to achieve better activation, lower series resistance and less dopant loss. For higher activation, the pre‐heat temperature of FLA was varied by 50 °C higher or lower than the desired base temperature. For lower resistance, the sidewall spacer thickness was reduced by 50 Å, 100 Å and 150 Å. For reducing dopant loss during the contact etch process, the deeper S/D Rp was used by increasing the S/D implant energy with an increased Rp by 150 Å, 200 Å and 250 Å. Results with FLA base show 13.4% improvement, and at the higher pre‐heat temperature, it can be improved to 16.9%. In conclusion, FLA can be one of the candidates for periperal transistor performance improvement of next generation DRAM device.
Direct Energy Transferred Rapid Thermal Process (RTP) Method and System for Semiconductor Fabrication1321(2011); http://dx.doi.org/10.1063/1.3548470View Description Hide Description
A direct energy transferred rapid thermal process (RTP) method is proposed as a new generation RTP to overcome the issues of the conventional RTP and flash‐ or laser‐based anneals. Plasma immersion ion implantation (PIII) is utilized to realize the concept because it can deliver high power density. The ramp‐up rates between 100 °C/sec and ∼2000 °C/sec and the effective thermal budgets between seconds and milliseconds can be achieved with other advantages, including no pattern effect, low temperature annealing, high throughput, and flexible process controllability.
1321(2011); http://dx.doi.org/10.1063/1.3548471View Description Hide Description
We applied as an alternation of or to the implantation for source‐drain extension in pMOSFETs corresponding to various technology nodes from 65 nm to 28 nm. We could obtain identical or better characteristics compared to the cases of conventional ions. In addition, we found from blank wafer that larger impact damage to Si atoms in implantation leads to more advantageous in activation processing with only MSA.
1321(2011); http://dx.doi.org/10.1063/1.3548472View Description Hide Description
ClusterBoron implantation can be used effectively to reduce boron energy while keeping the ClusterBoron energy at a higher level to facilitate better beam transport. With the availability of ClusterBoron species like (referred as ) and (referred as ) along with ClusterCarbon species like (referred as ), it is possible to optimize the dose and energy for both ClusterBoron and ClusterCarbon species to obtain abrupt ultra‐low junction with enhanced boron activation. Cluster implant species ( and ) also provide self‐amorphization leading to amorphous Si layer. Heavier cluster species show larger amorphous layer thickness than the lighter ones for identical implant conditions. In this study we studied the difference between and process with and without a clustercarbon process for 500 eV monomer equivalent boron energies at a dose of The results show that both and process provide better Rs and junction characteristics. The main difference between these two cases is a lower sheet resistance with process when compared to by about 10%. At lower energy (<500 eV), the process show between 20% to 30% lowers Rs than Better self‐amorphization with than is attributed to the lower Rs with With good beam transport at lower energies, offers a production worthy process taking into account the process advantage too.