STRESS MANAGEMENT FOR 3D ICS USING THROUGH SILICON VIAS: International Workshop on Stress Management for 3D ICs Using Through Silicon Vias
1378(2011); http://dx.doi.org/10.1063/1.3615693View Description Hide Description
The concerns with managing mechanical stress distributions and the consequent effects on device performance and material integrity, for advanced TSV based technologies 3D are outlined. A model and simulation based Design For Manufacturability (DFM) type of a flow for managing the mechanical stresses throughout Si die, stack and package design is proposed. The key attributes of the models and simulators required to fuel the proposed flow are summarized. Finally, some of the essential infrastructure and the Supply Chain support items are described.
Multi‐Scale Environment For Simulation And Materials Characterization In Stress Management For 3D IC TSV‐Based Technologies—Effect Of Stress On The Device Characteristics1378(2011); http://dx.doi.org/10.1063/1.3615694View Description Hide Description
The paper addresses the growing need in a simulation‐based design verification flow capable to analyze any design of 3D IC stacks and to determine across‐die out‐of‐spec variations in device electrical characteristics caused by layout and through‐silicon‐via (TSV)/package‐induced mechanical stress. The limited test and characterization capabilities of 3D IC stacks and a strict “good die” requirement make this type of analysis really critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design‐for‐manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV‐based dies, stacks and packages. A set of physics‐based compact models for a multi‐scale simulation, to assess the mechanical stress across the device layers in silicon dies stacked and packaged with the 3D TSV technology, is proposed. A strategy for a materials data generation to feed simulation and a respective materials characterization approach are proposed, with the goal to establish a database for multi‐scale materials parameters of wafer‐level and package‐level structures. A proposal for model validation based and a calibration approach based on fitting the simulation results to measured local stress components and to electrical characteristics of the test‐chip devices are discussed.
1378(2011); http://dx.doi.org/10.1063/1.3615695View Description Hide Description
Thermo‐mechanical stresses are introduced in three dimensional integration structures employing TSVs during fabrication process. Stress analysis is required in order to manage the stress related performance and reliability issues in 3D TSV stacks. The TSV parasitic parameters need to be examined at the same time for system design optimization. In this paper, TCAD methodologies for process simulation, stress and parasitic modeling are demonstrated. The mechanical stress impact on the device performance and structural reliability for various materials and geometries is examined. The TSV parasitic parameters and their effects on performance are also analyzed. The correlation between these parameters is determined to achieve the design trade‐offs necessary for optimal 3D integration.
1378(2011); http://dx.doi.org/10.1063/1.3615696View Description Hide Description
The properties of the materials involved in the set‐up of 3D ICs need to be known, when the occurring mechanical stresses are to be modeled. Especially elastic‐plastic properties are relevant for the metal layers, which form redistribution layers and the through silicon vias. These can be characterized by the nanoindentation experiment, which is an established technique for the determination of Hardness and Young’s modulus of thin films. But this standard data set is not sufficient to be used as input to finite element simulations, because stress strain curves are required for the analysis of reliability of metal layers. These stress‐strain curves can be obtained by fitting the force displacement curves of the experiment with a finite‐element model. This approach enables additionally a solution for the so called substrate effect, because the stiffness of the substrate can be considered in the fitting model. This known approach is being applied and tested on thin (300 nm) gold layers deposited on silicon. It is shown that a good sensitivity for Young’s Modulus can be reached even for indents that exceed 10% of the film thickness, but for the plastic data the results are not unique and a range of plastic properties can be fitted.
Determination Of Thermal And Mechanical Properties Of Packaging Materials For The Use In FEM‐Simulations1378(2011); http://dx.doi.org/10.1063/1.3615697View Description Hide Description
Conventional and future electronic packages merge several different materials. Polymers, metals, solders, dielectrics, glasses, silicon, composites come together and show strong mechanical and material interaction. These interfacial effects increase if the miniaturization and diversification keep on rising as it is proposed. Many efforts have to be done to assure the system reliability of new electronic packages. The Finite Element Simulation has the ability to support the development process of new packages. The application of the FEM‐analysis requires the knowledge about the precise mechanical and thermal behaviour of the materials. The paper presents different measurement methods to determine accurate mechanical material properties of moulding compound polymers, underfillers, solder mask, and wafer photo resist and solder joints. The temperature dependency is essential to be respected. The polymer materials moulding compound as well as solder mask were characterized by Dynamic Mechanical Analysis under humidity influences to determine mechanical properties as function of moisture and temperature. Further experiments on polymer were conducted to extract the cure kinetics by Differential Scanning Calorimetry and to determine Bulk Modulus by Pressure‐Volume‐Temperature experiments (PVT). Altogether, these material properties need to be modeled in a comprehensive way fitting to each other. The common practice of just compiling data from different sources has been found to fail yielding in reliable and accurate results. The conditions under which the data were determined may cause mismatches between them and cause inconsistencies within the model. If a convergent solution was obtained at all, much simulation time would be needed as many iterations with small time steps were needed. In order to avoid this, the paper reports an approach of characterizing the temperature and time dependent mechanical material properties in one comprehensive scheme. The solder measurement allows the determination of material properties within a temperature range of Further, the time dependent creep deformation can be measured within a strain‐rate range of Solder alloys based on Sn‐Ag/Sn‐Ag‐Cu with additionally impurities and joint sizes down to O/ 200 μm were investigated. To finish the material characterization process the material model coefficient were extracted by FEM‐Simulation to increase the accuracy of data.
Multi‐Scale Mechanical Probing Techniques To Investigate The Stability Of BEOL Layer Stacks With Sub‐100 nm Structures1378(2011); http://dx.doi.org/10.1063/1.3615698View Description Hide Description
The stress levels induced by chip‐package interaction (CPI) impose an increased risk of mechanical failure on advanced backend‐of‐line (BEOL) layer stacks in microelectronic circuits if they contain fragile ultralow‐k (ULK) interlayer dielectric (ILD) films. On the one hand, multilevel finite element modeling is used to assess the potential risk at an early stage of the development of new microelectronic products. On the other hand, the theoretical models need as accurate as possible materials parameters as an input to provide realistic results. Moreover, it is highly desirable to have multi‐scale experimental probes available which can provide complementary data to support the modeling calculations. The present paper provides an overview about various mechanical probing techniques which operate on the scale of less than 100 nm up to more than 100 μm. In this way, typical feature sizes are covered which occur from the package level via solder bumps or copper pillars down to small Cu/ULK interconnect structures. The experimental approaches are based on nanoindentation with lateral force detection and in‐situ scanning probe microscopy (SPM) imaging capabilities, and they include a novel technique named bump assisted BEOL stability indentation (BABSI) test. Especially, the interrelation between small‐scale mechanical properties of ULK dielectric films and stresses acting on larger scales are quantitatively assessed by means of the experimental approaches described here.
1378(2011); http://dx.doi.org/10.1063/1.3615699View Description Hide Description
This paper presents the results of nanoindentation experiments on Cu single crystals and Cu grains in through silicon via (TSV) structures used for 3D integrated circuit (IC) stacking, at sub‐10 nm and several‐10 nm penetration depths. The reduced moduli for Cu single crystals change from an average value to the uni‐directional values, as the penetration depths decrease from several‐10 nm to sub‐10 nm. At sub‐10 nm deformation, about one third of the indentations on Cu(111) and Cu(110) show fully elastic behavior, while all indentations on Cu(100) shows elastic‐plastic behavior. The reduced modulus values extracted from indents on Cu(111) and Cu(110) with fully elastic behavior are about 195 GPa and 145 GPa, respectively. For penetration depths of several‐10 nm up to 50 nm, the reduced modulus for Cu(100) varies between 50 GPa to 100 GPa. The averaged reduced moduli determined at relatively large penetration depths are explained with lattice rotation beneath the indentations. Since the activation of multiple slip systems is required for lattice rotation, the transition of the unidirectional reduced modulus to the averaged value with increasing penetration depths occurs differently for Cu(111) and Cu(100). Similar to the results from Cu single crystals, unidirectional reduced moduli are obtained for the Cu grains in TSV structures at sub‐10 nm penetration depths.
1378(2011); http://dx.doi.org/10.1063/1.3615700View Description Hide Description
In semiconductor devices, single crystal silicon (SCSi) is widely used. Si‐Doping (n or p), processing and structuring influences the quality of the SCSi. Multilayer deposition technologies are used. The partial or complete failure of devices is related to a change in the materials structural properties. The quality of the multilayer systems is also influenced by inter‐diffusion of elements which takes mainly place during processing. Microstructural characterization and quality control helps in understanding yield enhancements and failure modes. High Resolution X‐ray Diffraction (HRXRD) studies were carried out on SCSi‐based semiconductor devices. HRXRD are used to determine the stresses in SCSi devices. The stress state is directly related to the eventual device failure and influences its performance. As XRD is nondestructive, the fabrication processes could be accompanied. Corresponding to the need of semiconductors, XRD analyses can be provided for other (non‐SCSi) materials being used in the devices which comprise often complex material combinations. Phase analysis, texturing of phases and stresses in these polycrystalline phases are crutial for these systems as these criteria influence the device performances.
1378(2011); http://dx.doi.org/10.1063/1.3615701View Description Hide Description
This paper discusses Raman spectroscopy measurements of stress near Cu‐TSVs (Through Silicon Vias) used in 3D stacking of thinned chips. It discusses the resolution and penetration depth of the technique and the relation between the measured Raman shift and stress. Using a simple model, the various stress components near TSVs are discussed and the relation between the measured Raman shift and these stress components is analyzed. Results obtained on TSVs with nearby shallow‐trench isolation, with different Cu chemistry, with and without layer on top, and with different aspect ratio are discussed and analyzed using the simple model.
1378(2011); http://dx.doi.org/10.1063/1.3615702View Description Hide Description
Continuous scaling of on‐chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three‐dimensional (3‐D) integration with through‐silicon‐vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo‐mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3‐D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three‐dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi‐analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady‐state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop‐up due to interfacial fracture are discussed.
1378(2011); http://dx.doi.org/10.1063/1.3615703View Description Hide Description
Lab‐based Transmission X‐ray Microscopy and X‐ray Computed Tomography (TXM/XCT) with sub‐100 nm resolution are evaluated for their application in process and quality control in microelectronics, particularly for TSV characterization. These are the techniques of choice to localize defects in copper TSVs for 3D IC integration. In contrast to other techniques like Focused Ion Beam cross‐sectioning and subsequent Scanning Electron Microscopy imaging, the region of interest, i.e. the TSV, is imaged nondestructively and three dimensionally. For flat samples like thinned wafers, the tilted rotational axis tomography is proposed instead of the limited angle tomography since the better in‐plane resolution increases the quality of the resulting tomogram. Yield‐ and reliability‐limiting processes in 3D TSV technology like voids and incomplete filled vias can be made visible for an array of adjacent TSVs during one measurement without affecting the TSV.