CHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY 2005
788(2005); http://dx.doi.org/10.1063/1.2062933View Description Hide Description
Fostering innovation and assuring manufacturability through collaboration are the keys to the future prosperity of the semiconductor industry. To survive and prosper, all of us must participate in broad collaborations that maximize R&D efficiencies and spread out the ever‐rising costs of technical research and development. New and exciting collaborations are taking place throughout the industry as organizations — chipmakers, suppliers, universities, governments, consortia — experiment with new ways of cooperating with one another to achieve economies of scale and to serve the industry at large. New initiatives at SEMATECH, including new subsidiaries and partnerships with regional governments, offer the kind of flexibility that we believe industry participants must demonstrate in order to stay competitive in the 21st century. This article outlines several new approaches to the challenges of innovation, manufacturability, and collaboration.
788(2005); http://dx.doi.org/10.1063/1.2062934View Description Hide Description
This paper provides an overview of the economic and technological factors which are driving the demand for new metrology and inspection equipment, the challenges and opportunities facing new companies in bringing such equipment to market, and the funding environment in which new companies must raise capital to finance their efforts. Seven metrology companies and one inspection equipment company that have received first‐time venture backing since 2000 are used to illustrate how these specialized businesses are launched and funded.
788(2005); http://dx.doi.org/10.1063/1.2062935View Description Hide Description
Although the rapid scaling of integrated circuit (IC) technology is a widely recognized phenomena, Hutchinson recently proclaimed that the semiconductor industry has entered the world of nanoelectronics. For the next fifteen years, the industry will be extending CMOS technology through new materials and device structures. The new transistor designs that enable this scaling will be referred to as non‐classical CMOS. The gate length of nanotransistors will shrink to less than 10 run over the next fifteen years. The electrical properties of nano‐transistors have moved into regime of short channel devices and will continue to migrate away from the well‐understood physics of long channel transistors. The number of transistors in a single IC is already approaching a number that results 2 billion functions per IC by 2010. The astoundingly small size and high density will challenge metrology and characterization and most certainly move measurement further into the world of nanotechnology.
788(2005); http://dx.doi.org/10.1063/1.2062936View Description Hide Description
As devices continue to get smaller, and thus the size of yield‐limiting particles decreases, it is necessary to be ale to detect smaller particles on silicon surfaces. The current minimum detectable diameter of widely used particle‐detection systems using 488nm wavelength Ar+ gas lasers is, under optimized conditions, 50–60nm on bulk‐silicon surfaces. The sensitivity for SOI wafers has been considerably lower than this level due to not only additional distracting optical reflections from Si/SiO2/Si interfaces within the SOI stack but also undesirable light scattering at the rough interfaces. Various challenges in meeting the smaller particle‐detection requirements specified in the ITRS will be presented. Using a 266nm solid‐state laser, we have developed a system with the capability of detecting 30–40nm particles on both unpatterned bulk‐silicon and SOI wafers.
Starting Materials and Functional Layers for The 2005 International Technology Roadmap for Semiconductors: Challenges and Opportunities788(2005); http://dx.doi.org/10.1063/1.2062937View Description Hide Description
The integrated circuit (IC) industry is in the midst of an explosive expansion of new materials, processes and tools utilized in the fabrication of ICs and, accordingly, there are a host of associated new challenges and opportunities. These include, for example, the implementation of 300mm diameter wafers, the drive to equivalent oxide thickness in the sub‐1.0 nanometer regime for high‐performance logic devices via high‐k gate‐dielectric materials and metal gate electrodes, strained silicon methodologies, the expanded utilization of silicon‐on‐insulator (SOI) materials, copper metallization, low‐k inter‐level dielectrics and a plethora of alternative transistor configurations in non‐classical CMOS device structures. We will discuss the implications of these advanced materials and device configurations on the International Technology Roadmap for Semiconductors (ITRS).
788(2005); http://dx.doi.org/10.1063/1.2062938View Description Hide Description
To remain competitive IC manufacturers have to accelerate the development of most advanced (CMOS) technology and to deliver high yielding products with best cycle times and at a competitive pricing. With the increase of technology complexity, also the need for physical characterization support increases, however many of the existing techniques are no longer adequate to effectively support the 65–45 nm technology node developments. New and improved techniques are definitely needed to better characterize the often marginal processes, but these should not significantly impact fabrication costs or cycle time. Hence, characterization and metrology challenges in state‐of‐the‐art IC manufacturing are both of technical and economical nature. TEM microscopy is needed for high quality, high volume analytical support but several physical and practical hurdles have to be taken. The success rate of FIB‐SEM based failure analysis drops as defects often are too small to be detected and fault isolation becomes more difficult in the nano‐scale device structures. To remain effective and efficient, SEM and OBIRCH techniques have to be improved or complemented with other more effective methods. Chemical analysis of novel materials and critical interfaces requires improvements in the field of e.g. SIMS, ToF‐SIMS. Techniques that previously were only used sporadically, like EBSD and XRD, have become a ‘must’ to properly support backend process development. At the bright side, thanks to major technical advances, techniques that previously were practiced at laboratory level only now can be used effectively for at‐line fab metrology: Voltage Contrast based defectivity control, XPS based gate dielectric metrology and XRD based control of copper metallization processes are practical examples. In this paper capabilities and shortcomings of several techniques and corresponding equipment are presented with practical illustrations of use in our Crolles facilities.
788(2005); http://dx.doi.org/10.1063/1.2062939View Description Hide Description
New metrology opportunities are constantly emerging as the semiconductor industry attempts to meet scaling requirements. The paper summarizes some of the key FEOL and BEOL needs. These must be weighed against a number of considerations to ensure that they are good opportunities for the metrology equipment supplier. The paper discusses some of these considerations.
788(2005); http://dx.doi.org/10.1063/1.2062940View Description Hide Description
High‐k gate stack fabrication via atomic layer deposition (ALD) of ultra thin HfO2 and HfxSi1−xO2 films is demonstrated utilizing metal‐amide precursors and ozone as an oxidant. High resolution transmission electron microscopy (TEM) shows that films near 2.0 nm are reproducible. X‐ray reflectivity (XRR) and Rutherford backscattering (RBS) indicate that this ALD chemistry proceeds similarly on multiple surface preparations including HF last without growth incubation. High field mobility of more than 85% of the universal SiO2 mobility has been achieved at EOT ∼1nm with a reduction of more than two orders of magnitude in leakage current density as compared with a SiO2/poly Si gate. Various ALD metal nitrides such as TiN, HfN, HfSiN have been deposited on HfO2 and HfSiOx dielectrics which enabled a study of the interfacial reaction between high‐k dielectrics and metal electrode materials. The thermal stability of PVD Ru deposited on ALD HfO2 has also been observed.
788(2005); http://dx.doi.org/10.1063/1.2062941View Description Hide Description
It is shown that inelastic electron tunnelling spectroscopy (IETS) is a powerful technique to study microstructures and defects in Metal‐Insulator‐Semiconductor (MIS) systems where the insulator is sufficiently thin to allow significant tunnelling current to flow through. The information that may be revealed by IETS contains a wide variety of inelastic interactions, including interactions with phonons, various bonding vibrations, bonding defects, and impurities. Examples will be given to illustrate the capabilities of this technique.
Atomic and Electronic Structure Investigations of HfO2/SiO2/Si Gate Stacks Using Aberration‐Corrected STEM788(2005); http://dx.doi.org/10.1063/1.2062942View Description Hide Description
Aberration correction in scanning transmission electron microscopy represents a major breakthrough in transmission electron microscopy, enabling the formation of sub‐Angstrom probe sizes. Thus, electron microscopy achieved single atom sensitivity. Here, we show how this technique with its unique spatial resolution in combination with high‐resolution electron energy‐loss spectroscopy can be used to investigate atomic and electronic structures of semiconductor interfaces with single atom sensitivity. We employ a Si/HfO2/SiO2/Si high‐k dielectric interface to show the presence of single Hf atoms in the SiO2 interlayer. Furthermore, we demonstrate how local dielectric properties and local band structure information can be obtained by electron energy‐loss spectroscopy.
788(2005); http://dx.doi.org/10.1063/1.2062943View Description Hide Description
Photoelectron spectroscopy is a powerful technique for the analysis of gate dielectrics because it can determine the elemental composition, the chemical states, and the compositional depth profiles non‐destructively. The sampling depth, determined by the escape depth of the photoelectrons, is comparable to the thickness of current gate oxides. A maximum entropy algorithm was used to convert photoelectron collection angle dependence of the spectra to compositional depth profiles. A nitrided hafnium silicate film is used to demonstrate the utility of the technique. The algorithm balances deviations from a simple assumed depth profile against a calculated depth profile that best fits the angular dependence of the photoelectron spectra. A flow chart of the program is included in this paper. The development of the profile is also shown as the program is iterated. Limitations of the technique include the electron escape depths and elemental sensitivity factors used to calculate the profile. The technique is also limited to profiles that extend to the depth of approximately twice the escape depth. These limitations restrict conclusions to comparison among a family of similar samples. Absolute conclusions about depths and concentrations must be used cautiously. Current work to improve the algorithm is also described.
The Relation Between Crystalline Phase, Electronic Structure, and Dielectric Properties in High‐K Gate Stacks788(2005); http://dx.doi.org/10.1063/1.2062944View Description Hide Description
As high permittivity dielectrics approach use in metal‐oxide‐semiconductor field effect transistor (MOSFET) production, an atomic level understanding of their electronic and dielectric properties is being rigorously examined. In our work we illustrate studies leading to such an understanding for the important materials HfO2 and ZrO2. Valence and conduction band densities of states for HfO2/SiO2/Si and ZrO2/SiOxNy/n‐Si structures were determined by soft X‐ray photoemission and inverse photoemission. First principles calculations were used to help in assigning valence band maxima and conduction band minima. The energies of defect states at the band edges were determined by comparing the theoretical and experimental results. From this information, we are able to show that both of these dielectric materials have high enough barriers for both electron and hole transfer. We show that the crystal structure in ultrathin ZrO2 films has considerable effects on permittivity as well as bandgap. The films reported here are predominantly amorphous below a critical thickness (∼5.4 nm) and transform to the tetragonal phase upon annealing, while thicker films appear tetragonal as grown. Finally, bandgaps obtained from combined PES and IPES studies were compared with the optical bandgap derived from ellipsometry measurements. The difference in the bandgap values found in this comparison can be attributed to the final state effects in the excitation processes of the spectroscopies involved. We discuss the interplay of the dielectric’s crystal phase, defects and electronic properties, as well as the impact of this understanding on possible tailoring of the film phase for improving band‐gap, band‐offset and leakage. Finally, we note that lack of sufficient understanding of the dielectric’s phase and electronic properties can have negative impact on the ability to correctly determine a film’s EOT.
788(2005); http://dx.doi.org/10.1063/1.2062945View Description Hide Description
65 nm and 45 nm silicon devices will utilize compositionally critical processes for gate dielectrics, capacitor dielectrics, gate and capacitor electrodes, and ultra shallow junction layers. For example, small changes in nitrogen composition have been correlated with unacceptable shifts in electrical properties of devices with SiOxNy gate dielectrics. Present optically‐based metrology technologies for such applications are reaching limits for precise thickness measurements and do not provide direct and adequately precise compositional information. As a result, mature analytical techniques, such as x‐ray photoelectron spectroscopy (XPS), are now being transitioned to in‐line production metrology usage.
We discuss the application of XPS optimized for 200/300 mm production to compositional and thickness metrology of SiOxNy and high k gate dielectrics, high k capacitor dielectrics, and new electrode materials. The development of optimized hardware, robust data analysis algorithms and high throughput, fully automated operation has led to production implementation of XPS in advanced logic applications. The precise correlation of plasma nitridation metrology data with electrical device parameters has proven valuable in detecting process drifts early in the process flow, without the need to prepare devices through the first metal layer for testing. High density maps of film thickness and composition have enabled optimization of oxidation, nitridation and post‐nitridation anneal processes for SiOxNy film production for 90 nm, 65 nm and below. High precision compositional and thickness metrology data for high‐k gate and capacitor dielectrics is also presented.
A New NIST Database for the Simulation of Electron Spectra for Surface Analysis (SESSA): Application to Angle‐Resolved X‐ray Photoelectron Spectroscopy of HfO2, ZrO2, HfSiO4, and ZrSiO4 Films on Silicon788(2005); http://dx.doi.org/10.1063/1.2062946View Description Hide Description
We describe a new NIST database for the Simulation of Electron Spectra for Surface Analysis (SESSA). This database provides data for the many parameters needed in quantitative Auger electron spectroscopy (AES) and X‐ray photoelectron spectroscopy (XPS). In addition, AES and XPS spectra can be simulated for layered samples. The simulated spectra, for layer compositions and thicknesses specified by the user, can be compared with measured spectra. The layer compositions and thicknesses can then be adjusted to find maximum consistency between simulated and measured spectra. In this way, AES and XPS can provide more detailed characterization of multilayer thin‐film materials. We report on the use of SESSA for determining the thicknesses of HfO2, ZrO2, HfSiO4, and ZrSiO4 films on Si by angle‐resolved XPS. Practical effective attenuation lengths (EALs) have been computed from SESSA as a function of film thickness and photoelectron emission angle (i.e., to simulate the effects of tilting the sample). These EALs have been compared with similar values obtained from the NIST Electron Effective‐Attenuation‐Length Database (SRD 82). Generally good agreement was found between corresponding EAL values, but there were differences for film thicknesses less than the inelastic mean free path of the photoelectrons in the overlayer film. These differences are due to a simplifying approximation in the algorithm used to compute EALs in SRD 82. SESSA, with realistic cross sections for elastic and inelastic scattering in the film and substrate materials, is believed to provide more accurate EALs than SRD 82 for thin‐film thickness measurements, particularly in applications where the film and substrate have different electron‐scattering properties.
788(2005); http://dx.doi.org/10.1063/1.2062947View Description Hide Description
ARXPS provides a non‐destructive method for producing depth profiles from ultra‐thin films such as transistor gate dielectrics. The generation of depth profiles from ultra‐thin films using ARXPS is not a direct process but involves calculating the ARXPS response from trial depth profiles and comparing this with the experimental data. The trial profile is then adjusted to improve the fit. This process is continued until the optimum fit is achieved. The profiles to be presented in this paper have been generated by a combination of maximum entropy, a genetic algorithm and Powell optimization; these processes are explained. The purpose of this paper is to assess the quality of the profiles produced, specifically for silicon oxynitride layers. A model oxynitride layer on silicon structure has been constructed. From that model, simulated angle resolved XPS data have been generated. The simulated data were then used to generate the depth profile using the techniques described above. Using this method, it is possible to assess the depth resolution of the method without the presence of any uncertainties regarding the sample. The reproducibility of the method and the effect of user‐selected parameters can also be assessed.
788(2005); http://dx.doi.org/10.1063/1.2062948View Description Hide Description
As the gate dielectric has scaled to the sub 3 nanometer regime, demands on gate dielectric thickness control have translated into the need for sub‐monolayer precision on thickness measurements. While current ellipsometry techniques are capable of meeting these requirements, environmental film growth on the gate dielectric induces changes in the optical thickness of the film, yielding artificially thick results when measured. This growth is not constant, and we will discuss how both large scale and localized fluctuations of ambient parameters affect growth rates and can destabilize existing growth.
In response to AMC (Airborne Molecular Contamination) layer formation, optical thickness metrology suppliers have developed a variety of techniques to remove the AMC layer from the film prior to measurement. As AMC growth rates are affected by humidity, air pressure, and air composition, each AMC desorption method must be customized for the individual properties of the gate dielectric and process environment to optimize AMC removal. Two AMC layer desorption techniques have been investigated and will be covered along with their respective strengths and complications in a production environment.
788(2005); http://dx.doi.org/10.1063/1.2062949View Description Hide Description
We demonstrate that by using a multi‐technology optical metrology platform, accurate and precise measurements may be obtained for both thickness and stoichiometry of advanced Gate materials, including in particular Nitrided Oxide and Hafnium Silicate. The method combines an ultra‐stable single‐wavelength ellipsometer (Therma‐Wave’s Absolute Ellipsometer®) with a spectral technique to measure the reflectance of the sample in the Deep Ultra‐Violet (DUV) part of the spectrum (down to 190nm). This exploits the fact that the non‐SiO2 components of these advanced Gate films, namely Silicon Nitride and Hafnium Oxide, are much more strongly absorbing in the DUV range than is SiO2 itself. Thus, by combining a DUV absorption measurement with a film‐thickness measurement made in the visible part of the spectrum, it is possible to decouple efficiently the thickness and stoichiometry measurements even for very thin (<15Å) Gate films.
788(2005); http://dx.doi.org/10.1063/1.2062950View Description Hide Description
We report on the use of two different optical metrology techniques for characterization of high‐k gate dielectrics. Spectroscopic Ellipsometry (SE) is a standard in‐line metrology technique used to extract film information such as thickness and optical constants. However, with the gate dielectric being extremely thin (∼3nm), SE encounters certain inherent limitations when it comes to the data analysis. As a result, SE requires a secondary technique to fully characterize the thin films. Therefore, the ability of Second Harmonic Generation (SHG) to serve as a complimentary optical technique is reviewed. This non‐linear optical technique probes the high‐k/silicon interface and demonstrates sensitivity towards certain process‐induced conditions such as chemical composition, phase separation, defect trap states, and interfacial roughness.
788(2005); http://dx.doi.org/10.1063/1.2062951View Description Hide Description
Metal electrode materials are being extensively evaluated as potential replacements for polysilicon in order to eliminate gate depletion, reduce gate resistance, overcome equivalent oxide thickness (EOT) scaling limitations and Fermi level pinning effects associated with the reaction between Hf‐based dielectric films and the polysilicon electrode. High‐angle annular dark field scanning transmission electron microscopy (HAADF‐STEM) using X‐ray spectra and electron energy loss spectra (EELS) were used to produce elemental profiles of dielectric and metal electrode constituents with particular emphasis on interfacial interactions. High spatial resolution chemical scan profiles of silicon, oxygen, nitrogen, and hafnium from the dielectric components in conjunction with various transition metals including hafnium, tantalum, molybdenum and ruthenium have been acquired to characterize the extent of material intermixing and crystallization as a function of deposition parameters and anneal temperature. The influence of the atomic percent Si in ternary compounds consisting of transition metal nitrides is presented within the context of Rutherford backscattering (RBS) composition data. Finally, factors influencing metal workfunction are presented based on physical and electrical characterization of high‐k capacitors and transistors.