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Virtual integrated processing for integrated circuit manufacturing
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10.1116/1.2731341
/content/avs/journal/jvsta/25/4/10.1116/1.2731341
http://aip.metastore.ingenta.com/content/avs/journal/jvsta/25/4/10.1116/1.2731341
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Linking of reactor (or wafer) scale and feature scale models for EP. Present case shows wafer-scale plating behavior (points, data; line, simulation; center at ; and edge at ) leading to drastically different feature scale gap-fill phenomena shown below with on-wafer location labels. SEM photos of feature cross section included at the center vs edge of the wafer for comparison.

Image of FIG. 2.
FIG. 2.

EP profile evolution showing bottom-up fill behavior near the bottom corner of features. Results normalized with reference length scale .

Image of FIG. 3.
FIG. 3.

(a) Instantaneous temperature distribution between pad and wafer surface based on frictional heating during polish. (b) Etch rate variation across wafer. (c) Molecular structures of the reaction with slurry to form on surface based on quantum-chemistry studies.

Image of FIG. 4.
FIG. 4.

Sample slurry transport simulations for CMP using a nitric-based slurry. Top: Top-down view of Cu ion concentration near the wafer surface. Bottom: Vertical cross section of Cu ion concentration field.

Image of FIG. 5.
FIG. 5.

(a) Layout for CMP simulation. (b) Evolution of surface topography from post-EP (topmost) to post-CMP shown along the cross section through the middle of the layout.

Image of FIG. 6.
FIG. 6.

CMP profile evolution, starting with a nonplanar EP topology, showing planarization and overpolishing behavior. Axes scaled with a reference length scale .

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/content/avs/journal/jvsta/25/4/10.1116/1.2731341
2007-07-02
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Virtual integrated processing for integrated circuit manufacturing
http://aip.metastore.ingenta.com/content/avs/journal/jvsta/25/4/10.1116/1.2731341
10.1116/1.2731341
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