Thin-film electronics by atomic layer deposition
(Color online) Schematics of test TFT Structures. (a) Bottom gate. (b) Top gate.
(Color online) Typical characteristics of an ALD-deposited ZnO TFT (from Ref. 11). Important characteristics are off-current, on-current, gate leakage, subthreshold slope, Vto, and field effect mobility extracted from the curve. Curves are shown for saturation (solid curve) and linear (crosses) regimes.
Characteristics of ZnO-based TFTs grown by ALD showing the improvement in turn-on voltage from a pure ZnO semiconductor (dotted curve) to a ZnO:N-doped semiconductor (solid curve), demonstrating nitrogen doping as a method to control charge carriers in ALD-deposited ZnO. Inset: Same data plotted as square root drain current. (Reprinted with permission from S. J. Lim, S. J. Kwon, H. Kim, and J. S. Park, Appl. Phys. Lett. 91, 183517 (2007). Copyright 2007, American Institute of Physics.).
Characteristics of ZnO-based TFTs grown by ALD showing the improvement in turn-on voltage comparing ZnO deposited by thermal ALD (TH-ALD) and ZnO deposited by oxygen plasma-assisted ALD (PE-ALD). Left axis: Drain current; right axis: square root drain current. (Reprinted with permission from D. Kim, H. Kang. J. M. Kim, and H. Kim, Appl. Surf. Sci. 257, 3776 (2011). Copyright 2011, Elsevier B.V.)
(Color online) ZnO-based SALD TFTs as a function of purge/reactant exposure time. Vto for devices made with short exposure time is acceptable (near 0 V), while longer exposure times typical of normal ALD chambers lead to very negative turn-on positions. Inset: Sheet resistance of 1000 Å thick ZnO films grown on glass with variation in ALD exposure time (see Ref. 44).
(Color online) Stability of ZnO TFTs made by spatial ALD under bias stress at room temperature with a 2 MV/cm field on the Al2O3 dielectric. (a) Unpassivated devices after 2.7 h (9600 s) stress; (b) Devices passivated with Al2O3 after 50 h (180 000 s) stress showing almost no shift. Drain current (Id) shown on logarithmic (left axis) and linear (right axis) scales (see Ref. 11).
(Color online) Drain current as a function of gate bias stress time for a top gate ZnO TFT grown by ALD with variations in the deposition conditions of the Al2O3 dielectric in contact with the ZnO semiconductor. Under an applied field of 1.4 MV/cm on the gate dielectric and 20 V drain voltage, the thermal ALD (flat curve commencing at Id ∼ 6×10−5 A) shows better stability than the O2 Plasma ALD (decaying curve commencing at Id ∼ 7×10−5 A). (Reprinted with permission from S. H. K. Park, C. S. Hwang, M. Ryu, S. Yang, C. Byun, J. Shin, J. I. Lee, K. Lee, M. S. Oh, and S. Im, Adv. Mater. 21, 678 (2009). Copyright 2009, Wiley-VCH Verlag GmbH & Co. KGaA.)
(Color online) Inhibition (selective deposition) of ZnO growth by thin layers of PMMA. ZnO growth is indicated by optical density at 355 nm. PMMA Inhibition layers of approximately 9, 18, and 38 Å tested.
(Color online) Images after (a) gate, (b) dielectric, (c) semiconductor, and (d) source drain deposition of a ZnO-based TFT deposited using the spatial ALD process with patterning entirely by printing of water-soluble deposition inhibitors (selective area deposition). Working devices with a saturation mobility of 2.7 cm2/Vs resulted.
(Color online) Variation of mobility as a function of process temperature for spatial ALD-deposited ZnO TFTs, demonstrating the potential to employ this process for low-temperature substrates. Included are devices constructed on Kapton and PEN at 150 °C.
(Color online) Ringing frequency (left axis) and propagation delay (right axis) as a function of supply voltage (Vdd) for seven stage ring oscillators employing SALD-deposited ZnO TFTs. The circuits achieved a propagation delay of 31 ns, indicative of low interface state density in ALD-deposited ZnO TFTs (see Ref. 51).
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