Simplified schematic illustration of the fabrication process for a DUV-MEMS stencil. (a) -thick LPCVD low-stress deposition, (b) exposure and development of using DUV lithography (minimum feature size is ), (c) dry etching transfer of the resist patterns into , (d) membrane etch window definition by backside lithography and pattern transfer, (e) KOH etching of the bulk until a -thick membrane is left, and (f) final membrane releasing using dry etching, membrane size is .
Scanning electron micrograph showing a micro/nano structure after dry etch transfer into the membrane. The left inlet shows a cross-section of the midprocess details of line patterns. The right inlet shows details of an electrode pattern at submicron scale. The etch profiles demonstrate the high selectivity and process control for the transfer of the -thick DUV resist pattern into the -thick layer.
(a) Optical image of a full wafer scale stencil containing various membranes, each containing numerous geometrical apertures, (b) released membrane containing simultaneous micro- and nano-apertures ranging from up to , and (c) released membrane containing micro- and nano-apertures ranging from up to (not shown).
Deposition process using a stencil. (a) The stencil is placed in contact or in close proximity to the substrate and a material is evaporated from a distant source and deposited through the apertures in the membrane onto the substrate, (b) the stencil is removed from the substrate, (c) and (e) the SEM-images show a stencil mask with a gap to a substrate after evaporation. The membrane in Fig. 4(c) has a gap of approximately , whereas a gap of approximately is observed in Fig. 4(e), and (d) and (f) the SEM-images show the corresponding Al pattern from Figs. 4(c) and 4(e).
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