Schematic of the MOS capacitor consisted of gate electrode, insulating thick gate hard mask, and thin gate spacer film. The notation , , , and are used to explain the experimental results in Sec. III.
Pattern structures of MOS capacitors, representing (a) the square-type area pattern and (b) the bar-type array pattern.
Gate oxide current–voltage plots of the gate MOS capacitors before∕after a constant current stress, compared with/without gate hard mask nitride.
Area dependence of the SILC showing the effects of the gate hard mask nitride film in the gated MOS capacitors. The capacitors with the dimensions of , , and are measured.
Conductance loss curves of the gate MOS capacitors with∕without the gate hard mask (HM) nitride.
Pattern-size dependent gate oxide SILC of gated MOS capacitors having the gate hard mask nitride and two different gate spacers (ON vs NON). The thin gate spacer and the thick spacer were applied in the cases of cell array and periphery patterns, respectively.
Pattern-size dependent interface trap density characteristics of gated MOS capacitors having gate hard mask nitride, where the effect of the gate spacer structures (ON vs NON) is compared.
High-resolution cross-sectional TEM images of the gate structure with (a) the large square-type area electrode and (b) the narrow bar-type cell array electrode. In the case of (b) cell array, the TEM sample was prepared by cutting in parallel to the wordline direction.
plots of the gated cell transistor with the different gate spacer structures before∕after F–N stress , which is equivalent to the current stress of for the large area MOS capacitors.
Transconductance degradation ratio of the gated cell transistor with the different gate spacer structures before∕after F–N stress.
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