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Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of gate MOSFET for high density DRAM applications
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10.1116/1.1897708
/content/avs/journal/jvstb/23/3/10.1116/1.1897708
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/23/3/10.1116/1.1897708
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Figures

Image of FIG. 1.
FIG. 1.

Schematic of the MOS capacitor consisted of gate electrode, insulating thick gate hard mask, and thin gate spacer film. The notation , , , and are used to explain the experimental results in Sec. III.

Image of FIG. 2.
FIG. 2.

Pattern structures of MOS capacitors, representing (a) the square-type area pattern and (b) the bar-type array pattern.

Image of FIG. 3.
FIG. 3.

Gate oxide current–voltage plots of the gate MOS capacitors before∕after a constant current stress, compared with/without gate hard mask nitride.

Image of FIG. 4.
FIG. 4.

Area dependence of the SILC showing the effects of the gate hard mask nitride film in the gated MOS capacitors. The capacitors with the dimensions of , , and are measured.

Image of FIG. 5.
FIG. 5.

Conductance loss curves of the gate MOS capacitors with∕without the gate hard mask (HM) nitride.

Image of FIG. 6.
FIG. 6.

Pattern-size dependent gate oxide SILC of gated MOS capacitors having the gate hard mask nitride and two different gate spacers (ON vs NON). The thin gate spacer and the thick spacer were applied in the cases of cell array and periphery patterns, respectively.

Image of FIG. 7.
FIG. 7.

Pattern-size dependent interface trap density characteristics of gated MOS capacitors having gate hard mask nitride, where the effect of the gate spacer structures (ON vs NON) is compared.

Image of FIG. 8.
FIG. 8.

High-resolution cross-sectional TEM images of the gate structure with (a) the large square-type area electrode and (b) the narrow bar-type cell array electrode. In the case of (b) cell array, the TEM sample was prepared by cutting in parallel to the wordline direction.

Image of FIG. 9.
FIG. 9.

plots of the gated cell transistor with the different gate spacer structures before∕after F–N stress , which is equivalent to the current stress of for the large area MOS capacitors.

Image of FIG. 10.
FIG. 10.

Transconductance degradation ratio of the gated cell transistor with the different gate spacer structures before∕after F–N stress.

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/content/avs/journal/jvstb/23/3/10.1116/1.1897708
2005-05-25
2014-04-21
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WNx∕poly‐Si gate MOSFET for high density DRAM applications
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/23/3/10.1116/1.1897708
10.1116/1.1897708
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