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Interface configuration and Fermi-level pinning of fully silicided gate and high- dielectric stack
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10.1116/1.2198849
/content/avs/journal/jvstb/24/3/10.1116/1.2198849
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/24/3/10.1116/1.2198849

Figures

Image of FIG. 1.
FIG. 1.

(a) vs of four metal silicides on . The value is calculated by taking the geometric mean of and with various stoichiometries (x) between metal and silicon. (b) The parameter and the charge neutrality level on as a function of at .

Image of FIG. 2.
FIG. 2.

vs of on and HfAlON. The value of HfAlON is nearly identical to the calculated value of around 0.63 obtained from Eq. (2).

Image of FIG. 3.
FIG. 3.

Comparison of value of various gate electrodes on high- gate dielectrics. HfAlON with FUSI gate shows weak Fermi-level pinning, even though Si atoms are present at the interface of FUSI gate/HfAlON stack.

Tables

Generic image for table
TABLE I.

Comparison of and of each FUSI gate on . The values are obtained from the equation of where .

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/content/avs/journal/jvstb/24/3/10.1116/1.2198849
2006-05-10
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/24/3/10.1116/1.2198849
10.1116/1.2198849
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