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Interface configuration and Fermi-level pinning of fully silicided gate and high- dielectric stack
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10.1116/1.2198849
/content/avs/journal/jvstb/24/3/10.1116/1.2198849
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/24/3/10.1116/1.2198849
/content/avs/journal/jvstb/24/3/10.1116/1.2198849
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/content/avs/journal/jvstb/24/3/10.1116/1.2198849
2006-05-10
2014-08-02
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/24/3/10.1116/1.2198849
10.1116/1.2198849
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