Growth rate of on Si and Ti on . Thickness ratio of to Ti is also shown at the right axis.
Redrawing of Fig. 1. The growth curve of Ti is shifted to the left by .
XRD spectra of phase at (a) different annealing temperatures and (b) different thicknesses. Deposition temperature of CVD Ti was .
AFM images of interface. The measurement was taken after removal of from Si substrate. (a) at , (b) at , (c) at , and (d) at .
TEM image of phase between Si substrate and bit line contact plug. The plug material is tungsten and TiN.
SIMS profiles of B concentration to the distance from the interface. Each symbol denotes the following was implanted and annealed at for , CVD Ti is deposited, CVD Ti is deposited and annealed at for , and PVD Ti is deposited and annealed at for .
Cumulative probabilities of contact resistance between bit line and -type Si. The contact size is . Each symbol denotes 0.81, 0.99, 1.21, and of CVD Ti and of PVD Ti. All the wafers were annealed at for .
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