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Synthesized processing techniques for monolithic integration of nanometer-scale hole type photonic band gap crystal with micrometer-scale microelectromechanical structures
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10.1116/1.2207154
/content/avs/journal/jvstb/24/4/10.1116/1.2207154
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/24/4/10.1116/1.2207154

Figures

Image of FIG. 1.
FIG. 1.

Integrated fabrication process flow for PhC with MEMS structures. Steps (a)–(c) describe the deposition of the metal electrodes and oxide hard mask layers. Steps (d)–(f) describe the PhC and MEMS comb drive critical dimension pattern definition and transfer process. Steps (g)–(i) describe the opening of large alignment structures, while steps (j)–(l) depict the oxide release and also postprocessing modules.

Image of FIG. 2.
FIG. 2.

(a) Illustration of resolution improvement through the reduction of optical lithographic wavelengths. (b) Off axis illumination of the annular and quadrupole schemes. (c) Phase shift masking technique with use of shifters within the glass mask. (d) Schematic of an on-axis illumination lithographic system for the depiction of maximum cone angles in the condenser and projection lens.

Image of FIG. 3.
FIG. 3.

Lithography experiment patterns with constant linewidths but different pattern density of line/space duty factors of (a) 1:3 and (b) 1:1, respectively.

Image of FIG. 4.
FIG. 4.

Critical dimension plots for lithographic experiments with a constant NA of 0.68 and varying coherence factors of 0.38, 0.45, and 0.51 for line patterns with duty factors of (a) 1:3 and (b) 1:1.

Image of FIG. 5.
FIG. 5.

SEMs of sublithographic wavelength exposure failures for (a) unresolved dense structures (b) and lifted off resist.

Image of FIG. 6.
FIG. 6.

Schematic illustration of layout vs lithographic variations due to (a) a pull-back mechanism at the line end and (b) a flaring mechanism at the end of connected lines, combined to the cause “necking.”

Image of FIG. 7.
FIG. 7.

(a) Patterns of critical linewidths with constricted “neck” interfaces. (b) Extreme constrictions leading to critical linewidth breakages at the structure interface.

Image of FIG. 8.
FIG. 8.

(a) Cubic PhC hole array patterns with areas of resist poisoning (missing holes in uniform hole arrays). (b) Unintended resonators form within the PhC hole lattice.

Image of FIG. 9.
FIG. 9.

(a) Top view of PhC hole lattice with the dashed line showing where the cross section was taken to yield, (b) cross sectional SEM of PhC with controlled etch/passivation parameters yielding vertical sidewall profiles.

Image of FIG. 10.
FIG. 10.

RIE lag by aspect ratio dependent effects in plasma etching as shown for the high density pattern on the left of the SEM and the large OTS opening on the right.

Image of FIG. 11.
FIG. 11.

Notching of a SOI wafer, as shown in the (a) SEM of PhC hole array etched into silicon and “etch stopped” at the buried oxide interface. (b) Schematic illustration of the charge buildup effect causing further incoming ions to be deflected onto sidewalls.

Image of FIG. 12.
FIG. 12.

Postprocessing for (a) device sidewalls with undulating time multiplexed sidewall scallop roughness. After the thermal oxidation, (b) sharp edges of the roughness on device sidewalls are visibly reduced.

Image of FIG. 13.
FIG. 13.

Peeling of electrode copper metallization after the buffered oxide etch and spin drying.

Image of FIG. 14.
FIG. 14.

(a) SEM of MEMS actuator comb drive fingers and folded suspension beams with PhC structures and OTS. (b) FIB milled PhC holes on the released critical dimension air bridge structure.

Image of FIG. 15.
FIG. 15.

MEMS comb drive voltage actuation experiment results of measured displacement plotted with theoretical simulations for progressively increased applied voltage till “pull-in” instability occurs.

Tables

Generic image for table
TABLE I.

Process constants required for theoretical resolution limits of 100, 200, and linewidths by deep ultraviolet optical lithography.

Generic image for table
TABLE II.

Etch and passivation time multiplexed reactive ion etching process parameters for various etch sidewell profiles of the sloped, retrograde, and vertical types.

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/content/avs/journal/jvstb/24/4/10.1116/1.2207154
2006-06-28
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Synthesized processing techniques for monolithic integration of nanometer-scale hole type photonic band gap crystal with micrometer-scale microelectromechanical structures
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/24/4/10.1116/1.2207154
10.1116/1.2207154
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