Process sequence of metal nanocrystal embedded MOS device.
Typical surface images of Co NP measured by (a) SEM and (b) AFM.
High resolution TEM images of MOS structure with Co NP. (a) Wide area and (b) enlarged cross-sectional TEM image when the sample consists of tunneling oxide NP ∕top gate oxide layers.
Typical curves for samples A (with Co NP) and B (without Co NP). (a) The curve of sample B (circle) shows no hysteresis, while the curve of sample A (square) presents a hysteresis. Positive and negative stresses indicate the electron and hole chargings of Co NP, respectively. (b) Typical curve of sample A annealed by the thermal annealing process.
Time dependence of capacitance shift at the zero gate voltage after electron (or hole) was stored in Co NP at room temperature. Inset image is an electron charge loss as a function of time for different tunneling oxide thicknesses (circle: and triangle: thickness).
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