Scanning force microscope measurements of EBID rectangles used for conductivity tests. Line scans are shown for a wide EBID line (a2) fabricated with dwell time (overview shown in (a1)) and a wide EBID line (b) fabricated with .
characteristic of a wide EBID rectangle (see insert) exposed using a dwell time of measured by a four point resistance measurement technique.
GDSII design (a) and a scanning electron microscope (SEM) micrograph (b) illustrating the EBID wiring process for a CNT. Automatic drift compensation enables a precise definition of the contact position even at low beam energies on an insulating surface.
SEM micrographs showing a two (a) and a three point (b) wiring of CNTs fabricated by EBID. The three point wiring has been used for the measurements given in Fig. 5.
Transistor characteristics of the CNT shown in Fig. 4(b) using EBID wiring, three point measurement, and a back gate ( ). Source-drain current vs gate voltage for various drain voltages is shown. The insert shows source-drain current vs voltage for various gate voltages.
(a) Schematic illustration of a NEMS device for mechanical and electromechanical measurements on CNTs. (b) NEMS structure consisting of suspended structures without and (c) with additional EBID leads.
Results for EBID resistance obtained with tungsten hexacarbonyl and a probe current of at for various exposure dwell times.
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