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Cryogenic etch process development for profile control of high aspect-ratio submicron silicon trenches
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10.1116/1.2402151
/content/avs/journal/jvstb/25/1/10.1116/1.2402151
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/25/1/10.1116/1.2402151

Figures

Image of FIG. 1.
FIG. 1.

(a) Typical ZEP-520A photoresist mask with submicron features after e-beam patterning, (b) cryogenic silicon etch sample after cleaving (ZEP-520A mask: opening), and (c) measured parameters: mask opening width, depth, bottom trench width, undercut from which the sidewall angle is obtained, and width, measured from surface to give the effective sidewall angle.

Image of FIG. 2.
FIG. 2.

Open area etch depth vs time (base line process). Minimum etch depths of a few hundred nanometers can be obtained, allowing for accurate rib waveguide fabrication (inset).

Image of FIG. 3.
FIG. 3.

Measured parameters vs trench width for base line etch sample from Fig. 1(b): (a) etch depth and ARDE, (b) bottom trench width, (c) mask undercut, and (d) sidewall angle. The designation fifth, seventh, and ninth refers to the order of the silicon slab separating the trenches (e.g., fifth refers to ).

Image of FIG. 4.
FIG. 4.

Fine tuning individual etch parameters: (a) sample 7 (base line etch), (b) sample 9 , (c) sample 12 , (d) sample 13 (rf forward ), (e) sample 8 (rf forward ), (f) sample 10 , and (g) sample 14 (chamber ). All SEM’s show designed trenches with ninth-order silicon and first-order air DBR’s shown at 11 000 magnification.

Image of FIG. 5.
FIG. 5.

Measured parameters vs trench width for etch samples from Fig. 4(e) (rf forward ), Fig. 4(g), and Fig. 4(f) (chamber ): (a) etch depth and ARDE, (b) bottom trench width, (c) mask undercut, and (d) effective sidewall verticality, measured from trench bottom to from surface.

Image of FIG. 6.
FIG. 6.

Cross section of silicon DBR test structures with air gap: (a) -order silicon slabs (inset: detail of sidewall roughness at 150 000 magnification) and (b) -order silicon slabs. The air gaps are nominally and the silicon slabs are , where , is the DBR mirror order for the silicon slab (in this case or 7) and .

Image of FIG. 7.
FIG. 7.

(a) Silicon-on-insulator (SOI) Fabry-Pérot cavity integrated on a wide rib waveguide with deep etched silicon/air DBR’s, (b) cleaved facet of SOI rib waveguide showing expected location of optical power (dashed line), (c) measured Fabry-Pérot resonance spectrum, and (d) detail of resonance width (FWHM) at .

Tables

Generic image for table
TABLE I.

Baseline cryogenic etch process parameters (Oxford Plasmalab 100 ICP/RIE).

Generic image for table
TABLE II.

Summary of mask undercut and sidewall angle for recipes and samples shown in Figs. 4(a)–4(d), in which a single process parameter was varied.

Generic image for table
TABLE III.

Summary of mask undercut, sidewall angle, and effective verticality for recipes and samples shown in Figs. 4(e)–4(g), in which a single process parameter was varied.

Generic image for table
TABLE IV.

Summary of mask undercut, sidewall angle, and effective verticality for samples in which two process parameters were varied. The helium backing pressure was ; measurements refer to (designed) trenches for -, seventh-, and ninth-order silicon slabs.

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/content/avs/journal/jvstb/25/1/10.1116/1.2402151
2006-12-28
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Cryogenic etch process development for profile control of high aspect-ratio submicron silicon trenches
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/25/1/10.1116/1.2402151
10.1116/1.2402151
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