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Transport properties of InAs nanowire field effect transistors: The effects of surface states
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View: Figures


Image of FIG. 1.
FIG. 1.

FE-SEM image of InAs NWs grown on substrates. Top inset is the equivalent capacitance circuit where and are associated with the interface trap density. Bottom inset is equivalent dc circuit model for the underlap top-gate NWFET.

Image of FIG. 2.
FIG. 2.

Time-resolved transfer characteristics of an InAs NWFET with , , and , showing long characteristic time constants up to (open circles) and stretched exponential fits to these curves (solid lines).

Image of FIG. 3.
FIG. 3.

2D Silvaco Atlas simulation of the carrier concentration for a diameter InAs NWFET with (a) fixed positive charged traps under the gate and (b) charge neutral surface under the gate. and .

Image of FIG. 4.
FIG. 4.

(a) Transfer curves of an InAs NWFET with , , and , plotted for different gate voltage sweep rates. (b) Computed and from the transfer curves in (a).

Image of FIG. 5.
FIG. 5.

for an InAs NWFET device with , , and . [(a)–(c)] Hysteresis plots for fast gate voltage sweep rate . [(d)–(f)]. Hysteresis plots with a slower gate voltage sweep rate of .


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Transport properties of InAs nanowire field effect transistors: The effects of surface states