The schematic plots of the fabrication process of carbon nanotube devices. (a) Deposition of silicon oxide as the insulating layer. (b) Deposition of the barrier layer (TiN), the catalyst (Ni), and the electrode metal (Ti). (c) Lithographic steps to open the gap between metal islands. (d) Thermal CVD growth of carbon nanotubes.
TEM images of (a) middle and (b) tip sections of a carbon nanotube.
FESEM images of device M2 chosen from process run R2. There is only one bridging nanotube connecting the metal islands. The bridging nanotube is also shown in the inset.
FESEM images of device SM5 chosen from process run R5. There are only two bridging nanotubes. The two bridging nanotubes are labeled by (a) and (b), and are shown in the insets.
Raman spectra of the five process runs, R1, R2, R3, R4, and R5. The ratio is around .
Transfer characteristics of metallic devices M2 and M1, and mixed device SM5. The inset is the illustrative plot of mixed device SM5, which has one -CNT and one -CNT as the bridging nanotubes.
Transfer characteristics of purely semiconductive devices S5 and S3 are plotted. The insets show the device structures.
Schematic plot of (a) the purely semiconductive device and (b) its band diagram.
Process conditions with yields of sparse suspended nanotube devices are given in this table. The process conditions are labeled by R1, R2, R3, R4, and R5.
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