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Fabrication of terahertz holograms
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10.1116/1.2799976
/content/avs/journal/jvstb/25/6/10.1116/1.2799976
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/25/6/10.1116/1.2799976
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Example of a desired holograms (a array of spots) and (b) a grayscale representation of the relief pattern required to produce the hologram. The element pattern is .

Image of FIG. 2.
FIG. 2.

Three masks that are required to make the eight-level hologram.

Image of FIG. 3.
FIG. 3.

Schematic of fabrication process flow for silicon master. (a) A thick Si wafer is used. (b) The wafer is sputter coated with and spin coated with SU8 resist. (c) After exposure and development of the SU8 the is etched away. (d) The silicon is etched. (e) The SU8 is removed by lift-off of the remaining in HF. (f) Step (b) is repeated, but this time the planarization effect of the SU8 is exploited. (g) Steps (c) and (d) are repeated. (h) The result is a silicon master with a stepped relief. [(i)–(k)] A third masking stage is used to complete an eight-level structure by repeating the process steps for the preceding masks.

Image of FIG. 4.
FIG. 4.

(a) Optical micrograph showing the final polypropylene hologram made from the mask set shown in Fig. 2. The element is tilted to show the surface relief. Note that the lateral feature sizes are large compared to the pattern depth. (b) A scanning electron micrograph of a second more intricate pattern showing the surface relief more clearly.

Image of FIG. 5.
FIG. 5.

Schematic diagram of the experimental arrangement used to characterize hologram.

Image of FIG. 6.
FIG. 6.

Images of the terahertz beam (a) with and (b) without the hologram. Each image is approximately .

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/content/avs/journal/jvstb/25/6/10.1116/1.2799976
2007-12-10
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Fabrication of terahertz holograms
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/25/6/10.1116/1.2799976
10.1116/1.2799976
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