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Hybrid carbon nanotube-silicon complementary metal oxide semiconductor circuits
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10.1116/1.2800322
    + View Affiliations - Hide Affiliations
    Affiliations:
    1 Department of Electrical Engineering, Columbia University, New York, New York 10027
    2 Department of Applied Physics and Applied Mathematics, and Center for Electron Transport in Molecular Nanostructures, Columbia University, New York, New York 10027
    3 Department of Mechanical Engineering, and Center for Electron Transport in Molecular Nanostructures, Columbia University, New York, New York 10027
    4 Department of Electrical Engineering, Columbia University, New York, New York 10027
    5 Department of Applied Physics and Applied Mathematics, and Center for Electron Transport in Molecular Nanostructures, Columbia University, New York, New York 10027
    a) Electronic mail: inancmeric@cisl.columbia.edu
    b) Electronic mail: sw2128@columbia.edu
    J. Vac. Sci. Technol. B 25, 2577 (2007); http://dx.doi.org/10.1116/1.2800322
/content/avs/journal/jvstb/25/6/10.1116/1.2800322
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/25/6/10.1116/1.2800322
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Die photo of the test CMOS substrate, showing the available sites for tube transfer for hybrid circuit fabrication. (b) Schematic of the CNFET fabricated on the CMOS substrate. The FET is part of the chip commercially fabricated in technology.

Image of FIG. 2.
FIG. 2.

(a) SEM micrograph of grown two-nanotube bundle traversing the slit substrate. (b) Rayleigh scattering spectra for two-nanotube bundle used for fabrication of the CNFET -FET device. Inner peaks correspond to a (15,14) nanotube. Outer peaks correspond to (24,2) nanotube. Both tubes have diameter. (Based on analysis of the Rayleigh spectra as described in Ref. 9).

Image of FIG. 3.
FIG. 3.

(a) SEM micrograph of transferred nanotube before device fabrication. (b) Fabricated CNFET -FET device on the CMOS substrate.

Image of FIG. 4.
FIG. 4.

(a) Measured characteristics of the CNFET -FET integrated into the hybrid inverter. No saturation is evident in this plot as it is taken over a restricted range of . (b) The curve of the same CNFET.

Image of FIG. 5.
FIG. 5.

(a) Voltage transfer characteristic of hybrid CNFET/CMOS inverter operating at . (b) Supply current for the inverter as a function of .

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/content/avs/journal/jvstb/25/6/10.1116/1.2800322
2007-12-11
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Hybrid carbon nanotube-silicon complementary metal oxide semiconductor circuits
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/25/6/10.1116/1.2800322
10.1116/1.2800322
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