(a) Successive current-voltage characteristics obtained for sequential RVS on (50%Hf) gate stack with C-AFM tip as metal gate for nano-MOS. Forward/backward ’s indicated with arrows and with squares mark the current transport due to TAT. Only , , and no CL curves shown, respectively. (b) Fowler–Nordheim (FN/TUN) fit shown for no CL (unstressed/fresh) oxide spot curve. Inset (c) describes linearity for dominant FN tunneling domain (circle) (area of MOS: , 50%Hf).
(a) Current density vs gate voltage for temperature range of and (b) Arrhenius plots for Hf-based gate stack (80% Hf). Inset in (b) illustrates position of deep traps for substrate injection for low-field regime, , in the high- layer.
C-AFM constant voltage stress CVS (second scan) . (a) Topography, (b) current image, (c) relative FN, and (d) FL/frictional wear map. CVS scan (substrate injection) and a tip-surface contact force was used [, 50% Hf stack]. BD/stressed spots in circles resulted after a previous sequence of current limited RVS at different stressed spots as a function of CL. Tip offset between each BD spot used to observe charge lateral propagation. Current image correlates with topography; FN and FL features showing suppressed conductivity of stressed spots. Dark (low)-light (high) scaled: (a) , (b) , (c) , and (d) .
BD (areas/spots) lateral propagation comparison with absolute hillock height variation as a function of CL obtained after a successive sequence of RVS (pre-BD) applied as a function of current limit CL. A maximum with saturated confirms charge propagation prior to physical HBD of stack.
Trap generation trend as a function of current limit CL for (50%Hf). An increased/saturation indicated for TAT, SBD, and HBD phases.
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