Impact of a barrier on metal-oxide-semiconductor capacitor electrical properties
(Color online) Simulated current-voltage characteristics of 1 nm EOT and LAO gate stacks compared to 1 nm . Parameters used for simulations are metal gate work function ; : dielectric constant , effective electron mass , being the electron mass, band gap , potential barrier height at the silicon interface ; , , , ; , , , .
TEM image showing 3.8 nm of amorphous on 0.8 nm of crystalline on a Si(001) substrate. The entire stack presents abrupt interfaces.
(Color online) XPS spectra of core level (a) and LAO/Si samples before and after annealing in a tubular furnace under atmosphere at , (b) LAO/Si samples before and after annealing in a RTA furnace under atmosphere at 300, 400, 500, and , (c) samples before and after annealing in a RTA furnace under atmosphere at 300, 400, 500, and .
(Color online) Frequency measurements from 1 kHz to 1 MHz on as-deposited MOS capacitors.
(Color online) Comparison of experimental (1 MHz) and simulated characteristics of capacitors. (a) As-deposited and (b) after a PDA in a tubular furnace, .
(Color online) Comparison of experimental (1 MHz) and simulated characteristics of capacitors, as deposited and after a RTA annealing .
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