[(a)–(f)] Overview of the HSQ-based hybrid lithography process. (g) SEM images of a composite pattern printed using HSQ (1) and UV110G (2) on AR3G. The scale bar corresponds to . The region of interest (ROI) highlighted in (g) is shown in (h). The CD of the HSQ line is . The scale bar in (h) corresponds to . (i) SEM image showing an example of a two-level pattern after pattern transfer printed using HSQ and TDUR N700 showing (3) probing pads and (4) coarse interconnects printed by photolithography. The ROI highlighted in (i) is shown in (j), displaying (5) interconnects printed by EBL and (6) fill features printed by photolithography. The ROI in (j) is shown in (k), displaying (7) active area and (8) gate level features patterned with EBL. The scale bars in (i)–(j) are 10, 2, and , respectively.
(a) Process flow for the devices fabricated for this work. HSQ-based hybrid lithography and RIE were used to define active Si regions, referred to as fins. (b) A multilayer gate stack is deposited over the fins and patterned using HSQ-based hybrid lithography followed by RIE (b). (c) A SiN offset spacer was formed through chemical vapor deposition and RIE. Junction, silicide, contact, and wiring formation processes are not shown.
TEM and SEM images of completed devices. (a) Gate cross section obtained from devices with a gate pitch showing (1) BOX, (2) poly-Si, (3) SiN, (4) SOI fin, and (5) NiSi. The gate wraps around the fin, causing a projection of both the gate and fin in the channel regions. The gate length is . (b) Cross section through the fins in the gate stack region showing (6) TiN and high- gate dielectric stack. (c) Cross section through the fins in the source/drain region. (d) SEM image taken at 30° tilt from normal incidence with 45° substrate degree rotation revealing the intersection of the gate and the fin. The cross section locations of (a)–(c) are shown by (7)–(9), respectively. The scale bars shown in (c) and (d) are 50 and , respectively. Images (a)–(c) are shown at the same scale.
Source current, , vs gate voltage, , at a and drain-to-source bias, , from (a) -MOS and (b) -MOS devices working at a gate pitch. The width-to-length ratio of both transistors is . (c) Transfer curve from a CMOS inverter circuit contained within a SRAM bit cell with a cell area of . The cell was operated at . This cell features a gate pitch and a minimum fin pitch of . (d) SEM image showing the layout of (1) -MOS and (2) -MOS devices from an inverter within a SRAM cell. (e) SEM image showing the wiring and contacts for the SRAM bit cell. The input (4), (5), output (6), and ground (7) terminals for a single inverter are shown. The scale bar corresponds to .
Summary of ARC properties evaluated for HSQ-based hybrid lithography.
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