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Phase change memory technology
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10.1116/1.3301579
/content/avs/journal/jvstb/28/2/10.1116/1.3301579
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/28/2/10.1116/1.3301579

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Programming of a PCM device involves application of electrical power through applied voltage, leading to internal temperature changes that either melt and then rapidly quench a volume of amorphous material (reset), or which hold this volume at a slightly lower temperature for sufficient time for recrystallization (set). A low voltage is used to sense the device resistance (read) so that the device state is not perturbed.

Image of FIG. 2.
FIG. 2.

(Color online) Memory hierarchy in computers spans orders of magnitude in read-write performance, ranging from small amounts of expensive yet high-performance memory sitting near the CPU to vast amounts of low cost yet very slow off-line storage.

Image of FIG. 3.
FIG. 3.

(Color online) Qualitative representation of the cost and performance of various memories and storage technologies, ranging from extremely dense yet slow HDDs to ultrafast but expensive SRAM. is the size of the smallest lithographic feature. A smaller device footprint leads to higher density and thus lower cost.

Image of FIG. 4.
FIG. 4.

(Color online) Access times for various storage and memory technologies, both in nanoseconds and in terms of human perspective. For the latter, all times are scaled by so that the fundamental unit of a single CPU operation is analogous to a human making a 1 s decision. In this context, writing data to Flash memory can require more than “1 week” and obtaining data from an offline tape cartridge takes “1000 years” (Refs. 29 and 55).

Image of FIG. 5.
FIG. 5.

(Color online) Semiconductor device technology node is commonly described by the minimum feature size that is available via lithographic patterning. Thus the smallest device area that can be envisioned which is still accessible by lithographically defined wiring is . To increase effective bit density beyond this, either sublithographic wiring, multiple bits per device (analogous to MLC Flash technology), or multiple layers of stacked memory arrays are required, as described in Sec. V C.

Image of FIG. 6.
FIG. 6.

(a) Phase change nanoparticles of Ge–Sb with 15 at. % Ge, fabricated by electron-beam lithography, diameter of about 40 nm. (b) GeTe nanoparticles synthesized by solution-based chemistry, diameter of about 30 nm (Ref. 73). (c) Nanoparticles of Ge–Sb with 15 at. % Ge, fabricated by self-assembly based lithography and sputter deposition, diameter of about 15 nm. (d) Nanoparticles of Ge–Sb–Se, fabricated by self-assembly based lithography and spin-on deposition, diameter of about 30 nm.

Image of FIG. 7.
FIG. 7.

(Color online) (a) Relative change in reflectivity in percent of a crystalline Ge–Sb thin film with 15 at. % Ge as a function of laser power and duration. The film was first crystallized by heating it in a furnace for 5 min at . A first pulse of fixed time and power (100 ns, 50 mW) was applied to create melt-quenched spots in the crystalline film, and then a second laser spot of variable power and duration at the same location was used to recrystallize the amorphous spots. (b) Normalized change in reflectivity (in percent) integrated over a power range between 24 and 25 mW from (a) as a function of laser pulse length. The dots are experimental data, the line is a fit to , with being the time, , and . (c) Relative change in reflectivity in percent of an amorphous Ge–Sb thin film with 15 at. % Ge as a function of laser power and duration. Note that much longer pulses are required.

Image of FIG. 8.
FIG. 8.

(Color online) Crystal growth velocity (solid line) for GeSb as inferred by matching between simulation and empirical measurements. Low temperature crystal growth speed was measured by monitoring the slow growth of crystalline nuclei for growth-dominated (AIST) material (Ref. 93); high-temperature crystal growth speeds represent the best match between the measured optically induced recrystallization of amorphous marks on thin film GeSb and simulations of this process (Refs. 93 and 105).

Image of FIG. 9.
FIG. 9.

(a) Scanning electron microscope image of a phase change bridge and its TiN electrodes. (b) Cross-sectional transmission electron microscope image of a 3 nm thick GeSb bridge.

Image of FIG. 10.
FIG. 10.

(Color online) Reset current of doped-GeSb phase change bridge devices vs cross-sectional area defined by the lithographic bridge width and the ultrathin film thickness .

Image of FIG. 11.
FIG. 11.

(Color online) Back-of-the-envelope estimate for the expected pulse width and associated current density as function of the pitch of the active volume of the phase change material. Also shown are the empirical current densities for a phase change bridge device [ for a , bridge (Ref. 42), with the equivalent pitch for lithographic definition estimated to be pitch], and for a dash-type cell (plotted for an equivalent 45 nm pitch).

Image of FIG. 12.
FIG. 12.

(Color online) Phase change device archetypes: (a) A typical contact-minimized cell, the mushroom cell, forces current to pass through a small aperture formed by the intersection of one electrode and the phase change material. (b) A typical volume-minimized cell, the pore cell, confines the volume of the phase change material in order to create a small cross section within the PCM device.

Image of FIG. 13.
FIG. 13.

TEM cross sections of a mushroom cell PCM element in the (a) set state and (b) reset state. In the set state, the phase change material is polycrystalline throughout. In the reset state, a “mushroom cap” of amorphous phase change material restricts the current flow through the bottom electrode.

Image of FIG. 14.
FIG. 14.

(a) TEM cross section of a pillar cell with a FET access device. (b) Close-up TEM cross section of GST/TiN pillar. The simulated reset current dependence of this device is shown in Fig. 18(a).

Image of FIG. 15.
FIG. 15.

TEM cross section of a 45 nm bottom CD low aspect-ratio pore cell filled with a PVD GST process. The simulated reset current dependence of this device is shown in Fig. 18(b).

Image of FIG. 16.
FIG. 16.

Illustration of the -trench cell, showing two neighboring devices with a common top electrode (e.g., along the bit line). Current passes through an aperture which is limited in one dimension by the thickness of the underlying sidewall-deposited metal heater, and in the other dimension by the width of the narrow trench in which phase change material (here, GST) is deposited.

Image of FIG. 17.
FIG. 17.

TEM cross section of the dash-confined cell, showing devices fabricated by a spacer process that are only 7.5 nm wide, and 65 nm deep in the orthogonal direction.

Image of FIG. 18.
FIG. 18.

(Color online) (a) Reset currents for the pillar cell and the mushroom cell both show a strong dependence on the critical aperture size. (b) The pore cell reset current is both strongly dependent on the aperture size and shape (pore slope). (Figure 10 shows how the reset current of the bridge cell scales directly with the cross-sectional area of the phase change material.)

Image of FIG. 19.
FIG. 19.

(a) Collar process is used to create a sublithographically sized TiN bottom electrode. First, a lithographically defined hole of diameter is etched into a SiON/SiN stack. A first collar is formed by depositing a conformal SiON layer followed by a collar RIE step. A second collar is formed in the same manner. Next, the CVD TiN is deposited to fill the hole. Finally, a series of CMP and oxide etch back processes are performed, resulting in a cylindrical TiN bottom electrode. (b) A TiN ring electrode is constructed in a similar manner except that only a thin layer of CVD TiN is deposited into the hole, and then the center of the hole is filled with oxide. Original figure from Ref. 140.

Image of FIG. 20.
FIG. 20.

(a) Sublithographic and lithography-independent feature is fabricated using the keyhole-transfer process: (1) A lithographically defined hole is etched and (2) the middle layer is recessed. (3) A highly conformal poly-Si film is deposited, producing a sublithographic keyhole whose diameter is equal to the recess of the layer. (4) The keyhole is transferred into the underlying SiN layer to define a pore, followed by (5) removal of the and poly-Si. (6) The phase change and top electrode (TiN) materials are then deposited and the cell is patterned for isolation. (b) A SEM cross section corresponding to step (3), showing keyholes for two different sized lithographically defined holes. Since the keyhole size does not depend on lithography, the phase change CD can be successfully decoupled from any lithographic variability.

Image of FIG. 21.
FIG. 21.

Set resistance and reset resistance distributions as a function of the programming pulse width. In this example, while 100 ns is sufficient to set most of the cells to below , many cells still have a resistance greater than . However, extending the 50 ns reset pulse to 100 ns has no noticeable effect on increasing the resistance of the reset tail. GST refers to the phase change material used in this experiment, (Ref. 249).

Image of FIG. 22.
FIG. 22.

(Color online) Reset tail modulation by the quenching time . A long quench time results in a partial set of a small fraction of devices within a large array.

Image of FIG. 23.
FIG. 23.

Cycling performance of the set and reset states of a single PCM cell.

Image of FIG. 24.
FIG. 24.

(Color online) Resistance distribution of a four-level cell using single-pulse programming. Process-induced variations cause distributions to overlap because the same applied voltage pulse leads to different temperatures in different cells.

Image of FIG. 25.
FIG. 25.

(Color online) array (100 devices) test structure programmed into 16 levels. Tight, well-controlled distributions allow 4 bits/cell. Iterative adjustment of pulse slopes depending on the programmed resistances is one method for achieving narrow distributions.

Image of FIG. 26.
FIG. 26.

(Color online) Accelerated failure of a -trench PCM cell, showing a decrease in reset resistance as a function of time at .

Image of FIG. 27.
FIG. 27.

(Color online) Simulated temperature profiles for PCM devices (microtrench-type devices) for the 180 and 65 nm technology nodes. Note that while the transient temperatures become close to the steady-state temperature, the expected temperature rise at the neighboring device remains much lower than .

Image of FIG. 28.
FIG. 28.

(Color online) Set and reset resistances during cycling, illustrating the differences between failure by stuck set and by stuck reset.

Image of FIG. 29.
FIG. 29.

Cycling endurance as a function of pulse energy, showing that device endurance drops rapidly with prolonged exposure to high temperatures.

Image of FIG. 30.
FIG. 30.

Top-down TEM images of large phase change bridge devices (, bridges of 20 nm thick Ge-doped SbTe material), showing an polarity-dependent shift of the amorphous plug toward the anode .

Image of FIG. 31.
FIG. 31.

(Color online) WDS profiles of elemental concentration (Te, Sb, and Ge) along the length of a long bridge at (a) 0.17 ms and (b) 1.27 ms after melting was initiated by a voltage pulse, showing rapid desegregation of elements in the molten state.

Image of FIG. 32.
FIG. 32.

(Color online) Cycling of a pore-PCM GST device, showing a stuck-set failure after , followed by ten pulses of reverse polarity (and of slightly higher magnitude), which were proven sufficient to allow cycling to continue for another set-reset cycles.

Image of FIG. 33.
FIG. 33.

Two example families of electrical signals that can be used for MLC programming: (a) rectangular pulses and (b) variable slope pulses.

Image of FIG. 34.
FIG. 34.

Example distribution of the logarithm of the resistance for each of four possible stored levels, implementing 2 bit MLC. The distributions shown here would suggest a non-negligible probability of classification error.

Image of FIG. 35.
FIG. 35.

Distribution tightening by means of a write-and-verify procedure.

Image of FIG. 36.
FIG. 36.

(Color online) Distributions of four resistance levels immediately after programming after 400 h at room temperature and after an additional thermal annealing at for 12 h.

Tables

Generic image for table
TABLE I.

Some phase change material parameters and the device performance characteristics they influence.

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/content/avs/journal/jvstb/28/2/10.1116/1.3301579
2010-03-19
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Phase change memory technology
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/28/2/10.1116/1.3301579
10.1116/1.3301579
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