(Color online) Schematic cross-section of the TFT device. The channel oxide is ZnO and the gate oxide is . The cap oxide layer, if present, is also . All oxides were deposited in an ALD system.
Normalized thickness vs time in the developer (developer ma-D 332S from microresist technology) for the samples with various cap thicknesses.
Electrical characteristic (measured resistance as a function of the gap distance between the ohmic contacts) of the TLM structure for a sample with 0.5 nm cap. The sheet resistance is determined from the slope of the characteristic, and of the contact resistance is determined at the intercept of the characteristic with the vertical axis .
Drain current () vs drain voltage for TFTs (a) without cap, (b) with 0.5 nm cap, and (c) with 2 nm cap. The ZnO channel is 15 nm thick for all, and the gate voltage, , is 8 V for the top curve and steps in −1 V increments to pinch-off.
Drain current vs gate voltage of TFTs without cap (solid lines) and with 0.5 nm cap (dashed lines). The ZnO channel is 15 nm thick for both, and drain voltage, , is 7 V. Linear scale for is shown on the right vertical axis and log scale on the left axis.
Contact resistance (Rc) extracted from the measured TLM structures that were fabricated on samples with various cap layer thickness.
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